公开(公告)号：US20050288403A1

公开(公告)日：2005-12-29

申请号：US10516169

申请日：2003-05-27

申请人： Monica de la Cruz ,  Cindy Doumen ,  Klaus Keck-Antoine ,  Brian Johnson

发明人： Monica de la Cruz ,  Cindy Doumen ,  Klaus Keck-Antoine ,  Brian Johnson

IPC分类号： C08L23/12 ,  C08K5/13 ,  C08K5/3435 ,  C08K5/524 ,  C08L23/10 ,  C08L35/00 ,  D01F6/46 ,  C08K5/34

CPC分类号： C08K5/3435 ,  C08K5/13 ,  C08K5/524 ,  C08L23/10 ,  C08L35/00 ,  C08L2201/08 ,  C08L23/12 ,  C08L2666/04

摘要： A polypropylene composition comprises: (a) a first stabilising component consisting of 100 ppm or less based on the weight of the polypropylene of a phenolic antioxidant or a mixture of phenolic antioxidants; (b) a second stabilising component consisting of 500 to 1000 ppm based on the weight of the polypropylene of a phosphite antioxidant or a mixture of phosphite antioxidants; and optionally (c) a third stabilising component consisting of 100 ppm to 5000 ppm based on the weight of the polypropylene of a hindered amine light stabiliser or a mixture of such stabilisers. The polypropylene composition advantageously is in the form of fibres. A preferred phenolic antioxidant is 1,3,5-tris(4-tert-butyl-3-hydroxy-2,6 dimethylbenzyl)-1,3,5-triazine-2,4,6-(1H, 3H, 5H)-trione (Lowinox 1790). A preferred phosphite antioxidant is tris(2,4-di-t-butylphenyl) phosphite (Alkanox 240). A preferred optional hindered amine light stabiliser is dimethyl succinate polymer with 4-hydroxy-2,2,6,6-tetramethyl-1-piperidine (Lowilite 62).

摘要翻译： 聚丙烯组合物包含：（a）基于酚类抗氧化剂的聚丙烯或酚类抗氧化剂的混合物的重量为100ppm或更少的第一稳定组分; （b）基于亚磷酸酯抗氧化剂的聚丙烯或亚磷酸酯抗氧化剂的混合物的重量的500至1000ppm的第二稳定组分; 和任选地（c）由受阻胺光稳定剂的聚丙烯的重量或这种稳定剂的混合物的100ppm至5000ppm组成的第三稳定组分。 聚丙烯组合物有利地是纤维的形式。 优选的酚类抗氧化剂是1,3,5-三（4-叔丁基-3-羟基-2,6-二甲基苄基）-1,3,5-三嗪-2,4,6-（1H，3H，5H ）-trione（Lowinox 1790）。 优选的亚磷酸酯抗氧化剂是三（2,4-二叔丁基苯基）亚磷酸酯（Alkanox 240）。 优选的可选受阻胺光稳定剂是具有4-羟基-2,2,6,6-四甲基-1-哌啶（Lowilite 62）的琥珀酸二甲酯聚合物。

公开(公告)号：US06930955B2

公开(公告)日：2005-08-16

申请号：US10851081

申请日：2004-05-24

申请人： Brian Johnson ,  Brent Keeth ,  Feng Lin

发明人： Brian Johnson ,  Brent Keeth ,  Feng Lin

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C11/4076

摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.

摘要翻译： 一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。 在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。 一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。 内部读延迟值用于抵消DRAM电路的内部读延迟。 一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

公开(公告)号：US06894551B2

公开(公告)日：2005-05-17

申请号：US10656987

申请日：2003-09-05

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G06F1/06 ,  H03H11/16

CPC分类号： G11C7/22 ,  G06F1/06 ,  G11C7/222 ,  H03K5/15013 ,  H03K2005/00286

摘要： Multiphase clock generators and methods are provided. A multiphase clock generator has a first clock divider for generating a first-phase clock signal from a first input clock signal. A first logic gate is connected to an output port of the first clock divider. A second clock divider is connected to an output port of the first logic gate. The second clock divider is for generating a second-phase clock signal from the first input clock signal. A second logic gate is connected to an output port of the second clock divider. A third clock divider is connected to an output port of the second logic gate. The third clock divider is for generating a third-phase clock signal from a second input clock signal.

公开(公告)号：US20050099103A1

公开(公告)日：2005-05-12

申请号：US10705037

申请日：2003-11-10

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： A47B81/00 ,  E05B15/00 ,  E05B15/16 ,  E05B17/20 ,  E05B65/00 ,  E05B65/44 ,  E05C3/04

CPC分类号： E05B17/2019 ,  E05B15/0053 ,  E05B65/0071 ,  E05B65/44 ,  E05B2015/165 ,  E05C3/041 ,  Y10T16/61 ,  Y10T70/5097 ,  Y10T292/1083

摘要： The present invention is directed to a lock for a cabinet of the type wherein a door of the cabinet is movable through a frame of the cabinet. An exemplary lock of the present invention includes a first and second restraining member connected by a rod and rotatable around an axis of rotation between a first position wherein a cabinet member is trapped between the restraining members and the door can not move through the frame and a second position wherein the door is freely movable through the frame. The lock optionally includes a mounting member having a rod-retaining section and optionally one or more rotation locks and/or one or more rotation restraints. The restraining members are optionally sized and shaped to facilitate rotation between the first and second position while accommodating different sizes and specifications of cabinet types. The lock optionally includes one or more strengthening members and end extensions angled on one or both ends of the rod. In additional embodiments of the present invention, the lock includes at least one friction pad for contacting a cabinet member and an adjustable connection between the rod and at least one restraining member.

摘要翻译： 本发明涉及一种用于这种类型的机柜的锁，其中机柜的门可通过机柜的框架移动。 本发明的示例性锁具包括第一和第二限制构件，其通过杆连接并且可绕第一位置旋转，第一位置和第二限制构件之间的限制构件和门之间的柜构件不能移动通过框架， 第二位置，其中门可自由移动通过框架。 锁可选地包括具有杆保持部分和可选地一个或多个旋转锁和/或一个或多个旋转限制器的安装构件。 限制构件可选地尺寸和形状以便于容纳不同尺寸和规格的柜类型的第一和第二位置之间的旋转。 锁可选地包括一个或多个加强构件和在杆的一端或两端成角度的端部延伸部。 在本发明的另外的实施例中，锁包括至少一个用于接触柜构件的摩擦垫和杆与至少一个限制构件之间的可调连接。

公开(公告)号：US06776567B2

公开(公告)日：2004-08-17

申请号：US10404797

申请日：2003-04-01

申请人： Brian Johnson ,  Edward Ng ,  Justin Mauck ,  Edward R. Dykes ,  Joseph Arthur Kraus

发明人： Brian Johnson ,  Edward Ng ,  Justin Mauck ,  Edward R. Dykes ,  Joseph Arthur Kraus

IPC分类号： B65G4907

CPC分类号： H01L21/67259 ,  H01L21/67126 ,  Y10S414/135 ,  Y10S414/136 ,  Y10S414/139

摘要： In a first aspect, a valve/sensor assembly is provided that includes a door assembly. The door assembly has (1) a first position adapted to seal an opening of a chamber; (2) a second position adapted to allow at least a blade of a substrate handler to extend through the opening of the chamber; and (3) a mounting mechanism adapted to couple the door assembly to the chamber. The valve/sensor assembly also includes a sensor system having a transmitter and a receiver adapted to detect a presence of a substrate and to communicate through at least a portion of the door assembly. Systems, methods and computer program products are provided in accordance with this and other aspects.

摘要翻译： 在第一方面，提供一种包括门组件的阀/传感器组件。 门组件具有（1）适于密封腔室的开口的第一位置; （2）第二位置，其适于允许至少一个衬底处理器的刀片延伸通过所述腔室的开口; 和（3）适于将门组件连接到腔室的安装机构。 阀/传感器组件还包括具有发射器和接收器的传感器系统，该发射器和接收器适于检测衬底的存在并且通过门组件的至少一部分进行通信。 根据本方面和其他方面提供系统，方法和计算机程序产品。

公开(公告)号：US06697297B2

公开(公告)日：2004-02-24

申请号：US10230673

申请日：2002-08-29

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

摘要： A system and memory including a circuit for setting write latency and a write/valid indicator. Time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. A write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

摘要翻译： 包括用于设置写延迟的电路和写/有效指示符的系统和存储器。 时间裕度区域刚好在第一或前沿之后并且恰好在时钟信号的前导码的第二或后沿之后建立，使得等待时间设置将被发现是不可接受的，如果其引起写入使能信号在这些区域中的任一个中转变 。 写入/有效指示电路通过延迟时钟信号或写入使能信号并分别将它们的定时与未延迟写入使能信号或时钟信号的定时进行比较来创建起始和结束时间余量区域。

公开(公告)号：US06683814B2

公开(公告)日：2004-01-27

申请号：US10278553

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06678600B2

公开(公告)日：2004-01-13

申请号：US10310119

申请日：2002-12-04

申请人： Otman A. Basir ,  Fakhreddine Karray ,  Wail Gueaieb ,  Brian Johnson

发明人： Otman A. Basir ,  Fakhreddine Karray ,  Wail Gueaieb ,  Brian Johnson

IPC分类号： B60R2132

CPC分类号： B60R21/01516 ,  B60R21/01556

摘要： A child seat detection system determines the presence of an infant seat and can distinguish between a forward-facing infant seat and a rearward-facing infant seat. The system determines the weight on a vehicle seat and compares the weight on the vehicle seat to a rear-facing infant seat maximum. If the weight on the vehicle seat exceeds the rear-facing infant seat maximum, the system determines whether a forward-facing infant seat is on the seat. If the weight on the vehicle seat does not exceed the rear-facing infant seat maximum, then the system determines whether a rear-facing infant seat is on the seat.

摘要翻译： 儿童座椅检测系统确定婴儿座椅的存在并且可以区分前向婴儿座椅和向后婴儿座椅。 该系统确定车辆座椅上的重量，并将车辆座椅上的重量与后面的婴儿座椅最大值进行比较。 如果车辆座椅上的重量超过了后面朝向的婴儿座椅最大值，则系统确定前方的婴儿座椅是否在座椅上。 如果车辆座椅上的重量不超过后面的婴儿座椅最大值，则系统确定后座婴儿座椅是否在座椅上。

公开(公告)号：US06587804B1

公开(公告)日：2003-07-01

申请号：US09637088

申请日：2000-08-14

申请人： Brian Johnson ,  Brent Keeth

发明人： Brian Johnson ,  Brent Keeth

IPC分类号： G06F112

CPC分类号： G11C29/028 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254

摘要： A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.

摘要翻译： 用于校准数字电路的数据路径的方法和装置使用偶数位伪随机校准模式。 在捕获周期中捕获图案的一部分，并用于预测校准图案的下一个到达部分。 捕获校准图案的下一个到达部分，然后在比较周期中与预测图案进行比较，并将比较结果用于到数据路径中的相对时间数据到数据中的时钟信号。 可以改变比较周期的持续时间以确保在校准过程中使用校准图案的所有可能位。

公开(公告)号：US6058444A

公开(公告)日：2000-05-02

申请号：US942878

申请日：1997-10-02

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4086

摘要： A self terminating electrical socket is described which adjusts communication line termination circuit characteristics in response to a mate engaging the socket. Electrical and mechanical detection techniques are described for switching the termination circuitry from a first state to a second state. The electrical socket is particularly well suited for use in a described memory bus. Multiple termination circuits are described which have different electrical characteristics depending upon the population of the electrical socket.

摘要翻译： 描述了一种自终端电插座，其响应于接合插座的配合来调节通信线路终端电路特性。 描述了用于将终端电路从第一状态切换到第二状态的电气和机械检测技术。 电插座特别适用于所描述的存储总线。 描述了多个终端电路，其根据电插座的总体具有不同的电特性。