公开(公告)号：US09204172B2

公开(公告)日：2015-12-01

申请号：US14683996

申请日：2015-04-10

Applicant: Apple Inc.

Inventor： Kenneth Greenebaum ,  Ian Hendry ,  Ian Ollmann ,  David Hayward ,  Brijesh Tripathi

IPC: G06K9/36 ,  H04N19/85 ,  G06T9/00 ,  H04N19/463 ,  G11B27/034 ,  H04N19/186 ,  H04N21/2343 ,  H04N21/2662 ,  H04N21/845 ,  H04N19/30

CPC classification number: H04N19/85 ,  G06T9/00 ,  G11B27/034 ,  H04N19/186 ,  H04N19/30 ,  H04N19/33 ,  H04N19/463 ,  H04N21/234327 ,  H04N21/2662 ,  H04N21/845

Abstract: Techniques are provided for encoding an extended image such that it is backwards compatible with existing decoding devices. An extended image format is defined such that the extended image format is consistent with an existing image format over the full range of the existing image format. Because the extended image format is consistent with the existing image format over the full range of the existing image format, additional image information that is included in an extended image can be extracted from the extended image. A base version of an image (expressed using the existing image format) may be encoded in a payload portion and the extracted additional information may be stored in a metadata portion of a widely supported image file format.

公开(公告)号：US09087393B2

公开(公告)日：2015-07-21

申请号：US13788209

申请日：2013-03-07

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Timothy J. Millet

IPC: G09G5/39 ,  G06T1/60

CPC classification number: G06T1/60 ,  G09G5/006 ,  G09G2340/0442 ,  G09G2340/0492 ,  G09G2360/125 ,  G09G2370/10

Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.

Abstract translation: 在一个实施例中，系统包括针对与网络显示器进行通信而优化的硬件。 硬件可以包括显示管单元，其被配置为将来自视频序列的一个或多个静态图像和一个或多个帧组合以形成用于由网络显示器显示的帧。 显示管单元可以包括写回单元，其被配置为将复合帧写回到存储器，可以使用视频编码器硬件来选择性地对帧进行编码，并将其分组化以便通过网络传输到网络显示器。 在一个实施例中，显示管单元可以被配置为在帧的生成期间向视频编码器发出中断，以重叠编码和帧生成。

公开(公告)号：US20150042659A1

公开(公告)日：2015-02-12

申请号：US13963511

申请日：2013-08-09

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Brijesh Tripathi

IPC: G09G5/00 ,  G06T3/40

CPC classification number: G09G5/006 ,  G06T3/4092 ,  G06T9/00 ,  G09G2340/02 ,  G09G2340/0407 ,  H04N19/124 ,  H04N19/134 ,  H04N19/182 ,  H04N19/184 ,  H04N19/186 ,  H04N19/90

Abstract: A method and device for data compression are presented, in which a data processor may receive a packet of image data which includes four groups of N bits, where N is an integer greater than 2. The data processor may compress the received packet of data, such that a total number of bits for the converted packet is less than four times N. The data processor may compress the received packet of image data by reducing the resolution of three of the values while maintaining the resolution of the fourth value. To reduce the resolution of the three values, the data processor may apply a dithering formula to the values. The data processor may then send the converted packet via an interface.

Abstract translation: 提出了一种用于数据压缩的方法和装置，其中数据处理器可以接收包括四个N位组的图像数据分组，其中N是大于2的整数。数据处理器可以压缩所接收的数据分组， 使得转换的分组的总比特数小于N倍。数据处理器可以通过在保持第四值的分辨率的同时降低三个值的分辨率来压缩接收的图像数据分组。 为了降低三个值的分辨率，数据处理器可以对该值应用抖动公式。 然后，数据处理器可以经由接口发送经转换的分组。

公开(公告)号：US20140173313A1

公开(公告)日：2014-06-19

申请号：US13717941

申请日：2012-12-18

Applicant: APPLE INC.

Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S. Thiara

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G09G5/00 ,  G09G5/006 ,  G09G5/18 ,  G09G2330/021 ,  G09G2370/10

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路和辅助链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令，辅助链路可指示主链路上的频率变化。 通过主链路到宿处理器的源处理器可以发送初始化参数，其可以包括时钟数据恢复锁定参数和空闲参数。

公开(公告)号：US20140139535A1

公开(公告)日：2014-05-22

申请号：US14163326

申请日：2014-01-24

Applicant: Apple Inc.

Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet ,  Brijesh Tripathi

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G09G5/39

Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

Abstract translation: 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。

公开(公告)号：US20210333132A1

公开(公告)日：2021-10-28

申请号：US17366459

申请日：2021-07-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal ,  Michael F. Culbert

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US11079261B2

公开(公告)日：2021-08-03

申请号：US16689555

申请日：2019-11-20

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US10789902B2

公开(公告)日：2020-09-29

申请号：US16113132

申请日：2018-08-27

Applicant: Apple Inc.

Inventor： Chaohao Wang ,  Brijesh Tripathi ,  Christopher Philip Alan Tann ,  David S. Zalatimo ,  Guy Cote ,  Hao Nan ,  Marc Albrecht ,  Paolo Sacchetto ,  Sandro H. Pintz

IPC: G09G3/36

Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.

公开(公告)号：US20200149932A1

公开(公告)日：2020-05-14

申请号：US16689555

申请日：2019-11-20

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F1/3206 ,  G06F13/16

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US10319333B2

公开(公告)日：2019-06-11

申请号：US13627885

申请日：2012-09-26

Applicant: Apple Inc.

Inventor： Brijesh Tripathi

IPC: G09G5/00

Abstract: In a graphics system, pixels may be provided to a graphics display at a pixel clock rate corresponding to an actual refresh rate nearest to and lower than a desired/target refresh rate. A number of additional pixels may be provided with the pixels for each image frame. The number is based at least on the actual refresh rate, target refresh rate, and a pixel-resolution of the image frame, such that providing pixels of an image frame and the number of additional pixels for each image frame at the pixel clock rate results in an effective refresh rate matching the target refresh rate. The additional pixels may be provided by adding one or more pixels at the end of each horizontal line of the image frame, or by adding an extra partial line in the vertical blanking interval. The additional pixels are not displayed and do not adversely affect normal operation.