公开(公告)号：US09864399B2

公开(公告)日：2018-01-09

申请号：US14965073

申请日：2015-12-10

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

公开(公告)号：US09779468B2

公开(公告)日：2017-10-03

申请号：US14816508

申请日：2015-08-03

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Arthur L. Spence ,  Gurjeet S. Saund ,  Robert P. Esser

IPC: G06T1/20 ,  G06F9/52 ,  G06F9/48 ,  G09G5/36 ,  G09G5/00 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06F9/52 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08 ,  Y02D10/24

Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.

公开(公告)号：US20160328322A1

公开(公告)日：2016-11-10

申请号：US14705506

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Harshavardhan Kaushikkar ,  Munetoshi Fukami ,  Gurjeet S. Saund ,  Manu Gulati ,  Shinye Shiu

IPC: G06F12/08 ,  G06F9/52

Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.

Abstract translation: 公开了一种用于处理来自计算系统中的功能单元的存储器请求的装置。 该装置可以包括可被配置为从功能接收请求的接口。 响应于确定接收到的请求是来自存储器的数据的请求，可以将电路配置为向存储器发起推测性读取访问命令。 电路还可以被配置为与推测性读取访问并行地确定如果推测性读取将导致排序或一致性违规。

公开(公告)号：US20160116969A1

公开(公告)日：2016-04-28

申请号：US14980912

申请日：2015-12-28

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Pulkit Desai ,  Rong Zhang Hu

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。

公开(公告)号：US20160091954A1

公开(公告)日：2016-03-31

申请号：US14499807

申请日：2014-09-29

Applicant: Apple Inc.

Inventor： Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Erik P. Machnicki ,  Keith Cox ,  Timothy J. Millet

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract translation: 公开了允许调整计算系统的性能设置的方法的实施例。 一个或多个功能单元可以包括多个监视器电路，每个监视器电路可以被配置为监视对应功能单元的给定操作参数。 在检测到与所监视的操作参数有关的事件时，监视器电路可产生中断。 响应于中断，处理器可以调整计算系统的一个或多个性能设置。

公开(公告)号：US09152588B2

公开(公告)日：2015-10-06

申请号：US13653151

申请日：2012-10-16

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Erik P Machnicki ,  Deniz Balkan

IPC: G06F13/24 ,  G06F13/26

CPC classification number: G06F13/24 ,  G06F13/26 ,  Y02D10/14

Abstract: In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.

Abstract translation: 在一个实施例中，系统包括耦合到外围设备的至少一个外围设备，中断控制器，存储器控制器，至少一个CPU以及中断消息电路。 中断消息电路可以被耦合以从外围设备接收中断信号，并且可以被配置为生成用于在通信结构上传输的中断消息。 在一些实施例中，可以存在多个外围设备，其具有通过该结构的独立路径，用于存储器操作到存储器控制器。 每个这样的外设可以耦合到中断消息电路的一个实例。 在一个实施例中，中断是电平敏感的。 中断消息电路可以被配置为向中断控制器发送中断设置消息中断清除消息以指示电平。

公开(公告)号：US09043632B2

公开(公告)日：2015-05-26

申请号：US13626522

申请日：2012-09-25

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Manu Gulati ,  Josh P. de Cesare

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F7/04 ,  H04N7/16 ,  G06F11/00 ,  G06F21/57 ,  G06F21/74 ,  G06F21/70 ,  G06F21/60 ,  G06F21/71

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/575 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/74

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包裹密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。

公开(公告)号：US20150134331A1

公开(公告)日：2015-05-14

申请号：US14109101

申请日：2013-12-17

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/06 ,  G10L19/26

CPC classification number: G10L15/28 ,  G06F1/32 ,  G06F1/3228 ,  G06F1/3287 ,  G06F3/165 ,  G10L15/22 ,  G10L25/48 ,  G10L2015/088 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个CPU，存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。 电路可以被配置为从麦克风接收音频样本，并且将这些音频样本与预定模式匹配，以检测来自包括SOC的设备的用户的可能命令。 响应于检测到预定模式，电路可以使存储器控制器上电，使得音频样本可以存储在与存储器控制器耦合到的存储器中。 该电路还可能导致CPU上电和初始化，并且操作系统（OS）可能引导。 在CPU正在初始化并且OS正在引导的时间内，电路和存储器可能正在捕获音频样本。

公开(公告)号：US20140108688A1

公开(公告)日：2014-04-17

申请号：US13653151

申请日：2012-10-16

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Erik P. Machnicki ,  Deniz Balkan

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F13/26 ,  Y02D10/14

Abstract: In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.

Abstract translation: 在一个实施例中，系统包括耦合到外围设备的至少一个外围设备，中断控制器，存储器控制器，至少一个CPU以及中断消息电路。 中断消息电路可以被耦合以从外围设备接收中断信号，并且可以被配置为生成用于在通信结构上传输的中断消息。 在一些实施例中，可以存在多个外围设备，其具有通过该结构的独立路径，用于存储器操作到存储器控制器。 每个这样的外设可以耦合到中断消息电路的一个实例。 在一个实施例中，中断是电平敏感的。 中断消息电路可以被配置为向中断控制器发送中断设置消息中断清除消息以指示电平。

公开(公告)号：US20140089682A1

公开(公告)日：2014-03-27

申请号：US13626566

申请日：2012-09-25

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Michael J. Smith ,  Shu-Yi Yu

IPC: G06F21/00

CPC classification number: G06F21/72 ,  G06F21/575

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包装密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。