Management of Data Storage in Memory Cells Using a Non-Integer Number of Bits Per Cell
    41.
    发明申请
    Management of Data Storage in Memory Cells Using a Non-Integer Number of Bits Per Cell 审中-公开
    使用非整数每个单元的位数来管理存储单元中的数据存储

    公开(公告)号:US20160012883A1

    公开(公告)日:2016-01-14

    申请号:US14858313

    申请日:2015-09-18

    Applicant: Apple Inc.

    Abstract: A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

    Abstract translation: 一种用于数据存储的方法包括:通过使用至少一个外部代码和一个内部代码对数据进行编码,以及在将编码数据存储在存储器单元中之前可选地反转编码数据,将数据存储在一组存储单元中。 从存储器单元读取编码数据,并将内码解码应用于读取的编码数据以产生解码结果。 根据内部代码的解码结果,至少部分读取数据有条件地反转。

    Configurable and low power encoder for cyclic error correction codes

    公开(公告)号:US09225359B2

    公开(公告)日:2015-12-29

    申请号:US13865345

    申请日:2013-04-18

    Applicant: Apple Inc.

    Inventor: Micha Anholt

    Abstract: A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols.

    DISTORTION CANCELLATION IN 3-D NON-VOLATILE MEMORY
    43.
    发明申请
    DISTORTION CANCELLATION IN 3-D NON-VOLATILE MEMORY 审中-公开
    三维非易失性存储器中的失败消除

    公开(公告)号:US20150332782A1

    公开(公告)日:2015-11-19

    申请号:US14811103

    申请日:2015-07-28

    Applicant: Apple Inc.

    Abstract: A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion.

    Abstract translation: 包括以三维(3-D)配置排列的多个模拟存储器单元的存储器中的方法包括识别潜在地对一组目标存储器单元造成干扰的潜在干扰存储器单元的多个组。 估计由目标存储器单元上的潜在干扰存储器单元的相应组造成的部分失真分量。 逐渐积累部分失真分量,以产生影响目标存储器单元的估计复合失真,同时仅保留复合失真而不保留部分失真分量。 读取目标存储器单元,并且基于估计的复合失真来消除目标存储器单元中的干扰。

    Error correction coding over multiple memory pages
    45.
    发明授权
    Error correction coding over multiple memory pages 有权
    通过多个内存页进行纠错编码

    公开(公告)号:US09136879B2

    公开(公告)日:2015-09-15

    申请号:US13921446

    申请日:2013-06-19

    Applicant: Apple Inc.

    CPC classification number: H03M13/29 G06F11/1012 G11C29/00 G11C2029/1804

    Abstract: A method for data storage includes encoding each of multiple data items individually using a first Error Correction Code (ECC) to produce respective encoded data items. The encoded data items are stored in a memory. The multiple data items are encoded jointly using a second ECC, so as to produce a code word of the second ECC, and only a part of the code word is stored in the memory. The stored encoded data items are recalled from the memory and the first ECC is decoded in order to reconstruct the data items. Upon a failure to reconstruct a given data item from a respective given encoded data item by decoding the first ECC, the given data item is reconstructed based on the part of the code word of the second ECC and on the encoded data items other than the given encoded data item.

    Abstract translation: 一种用于数据存储的方法包括使用第一纠错码(ECC)分别对多个数据项中的每一个进行编码,以产生相应的编码数据项。 编码数据项存储在存储器中。 多个数据项使用第二ECC共同编码,以便产生第二ECC的代码字,并且仅一部分代码字被存储在存储器中。 存储的编码数据项被从存储器调用,并且第一ECC被解码以便重构数据项。 在通过解码第一ECC无法从相应的给定编码数据项重构给定数据项时,基于第二ECC的代码字的部分和除了给定的编码数据项之外的编码数据项重建给定数据项 编码数据项。

    High-performance ECC decoder
    46.
    发明授权
    High-performance ECC decoder 有权
    高性能ECC解码器

    公开(公告)号:US09136871B2

    公开(公告)日:2015-09-15

    申请号:US14182802

    申请日:2014-02-18

    Applicant: Apple Inc.

    Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

    Abstract translation: 用于纠错码(ECC)解码的方法包括从表示已经用ECC编码的数据的一组位产生综合征。 错误定位器多项式(ELP)是基于综合征产生的。 识别至少一些ELP根,并校正由这些根指示的错误。 可以通过应用向量空间中的比特向量操作来产生每个综合征。 通过使用向量空间的不同基础应用向量运算来产生每个综合征。 可以通过使用串行乘法器对ELP系数进行操作,在给定的场元件上评估ELP,其中每个串行乘法器执行乘法循环序列,并在每个周期中产生中间结果。 响应于检测至少一个中期结果,指示给定的元素不是ELP根,在完成序列之前终止乘法循环。

    CONFIGURABLE AND LOW POWER ENCODER FOR CYCLIC ERROR CORRECTION CODES
    47.
    发明申请
    CONFIGURABLE AND LOW POWER ENCODER FOR CYCLIC ERROR CORRECTION CODES 有权
    用于循环错误校正码的可配置和低功率编码器

    公开(公告)号:US20140317478A1

    公开(公告)日:2014-10-23

    申请号:US13865345

    申请日:2013-04-18

    Applicant: APPLE INC.

    Inventor: Micha Anholt

    Abstract: A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols.

    Abstract translation: 一种用于编码的方法包括接收要用纠错码(ECC)编码的输入数据符号,以产生包括冗余符号的ECC的码字。 输入数据符号被应用于第一和第二处理级,使得第一处理级通过具有第一并行度的固定系数多项式执行第一多项式除法,并且第二处理级通过可配置 - 具有小于第一并行度的第二并行度的系数多项式,以便共同产生冗余符号。

    Chien search using multiple basis representation
    48.
    发明授权
    Chien search using multiple basis representation 有权
    Chien搜索使用多个基础表示

    公开(公告)号:US08739007B2

    公开(公告)日:2014-05-27

    申请号:US13895650

    申请日:2013-05-16

    Applicant: Apple Inc.

    Inventor: Micha Anholt

    Abstract: A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP.

    Abstract translation: 用于对纠错码(ECC)进行解码的方法包括接受在向量空间上定义的错误定位多项式(ELP)的至少第一和第二系数的系数,并且具有指示位置的至少一个根 在一组位中的错误,其表示已经用ECC编码的数据。 使用向量空间的第一基础来表示第一系数,并且使用与第一基础不同的向量空间的第二基础来表示第二系数。 使用处理电路,通过对系数应用代数运算来识别ELP的根,使得使用第一基础将代数运算应用于第一系数,并使用第二基应用于第二系数。 响应于ELP的确定的根而纠正错误。

    Configurable encoder for cyclic error correction codes
    49.
    发明授权
    Configurable encoder for cyclic error correction codes 有权
    用于循环纠错码的可配置编码器

    公开(公告)号:US08719678B2

    公开(公告)日:2014-05-06

    申请号:US14060748

    申请日:2013-10-23

    Applicant: Apple Inc.

    Inventor: Micha Anholt

    Abstract: Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode.

    Abstract translation: 用于编码的装置包括第一处理级,其被配置为使用属于表示第一ECC的第一生成多项式的第一组系数来过滤输入数据,以产生第一输出。 第二处理阶段被配置为使用属于商多项式的第二组系数来对第一输出进行过滤,商系多项式被定义为表示第二ECC的第二生成多项式的商除以第一生成多项式,以产生 第二输出。 辅助电路具有第一和第二操作模式,并且耦合到第一和第二处理级,以便当在第一模式下操作时,基于第一输出产生对应于第一ECC的第一冗余输出,并产生第二冗余输出 在第二模式下操作时,基于第二输出对应于第二ECC。

    High-performance ECC decoder
    50.
    发明授权
    High-performance ECC decoder 有权
    高性能ECC解码器

    公开(公告)号:US08700977B2

    公开(公告)日:2014-04-15

    申请号:US13920140

    申请日:2013-06-18

    Applicant: Apple Inc.

    Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

    Abstract translation: 用于纠错码(ECC)解码的方法包括从表示已经用ECC编码的数据的一组位产生综合征。 错误定位器多项式(ELP)是基于综合征产生的。 识别至少一些ELP根,并校正由这些根指示的错误。 可以通过应用向量空间中的比特向量操作来产生每个综合征。 通过使用向量空间的不同基础应用向量运算来产生每个综合征。 可以通过使用串行乘法器对ELP系数进行操作,在给定的场元件上评估ELP,其中每个串行乘法器执行乘法周期序列,并在每个周期中产生中间结果。 响应于检测至少一个中期结果,指示给定的元素不是ELP根,在完成序列之前终止乘法循环。

Patent Agency Ranking