OVERLAY ERROR CORRECTION
    41.
    发明申请

    公开(公告)号:US20170097576A1

    公开(公告)日:2017-04-06

    申请号:US14874353

    申请日:2015-10-02

    CPC classification number: G03F7/70633

    Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.

    RESIST HARDENING AND DEVELOPMENT PROCESSES FOR SEMICONDUCTOR DEVICE MANUFACTURING
    42.
    发明申请
    RESIST HARDENING AND DEVELOPMENT PROCESSES FOR SEMICONDUCTOR DEVICE MANUFACTURING 审中-公开
    用于半导体器件制造的耐腐蚀和开发工艺

    公开(公告)号:US20160329222A1

    公开(公告)日:2016-11-10

    申请号:US15216521

    申请日:2016-07-21

    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

    Abstract translation: 在一些实施例中,提供了在衬底上形成蚀刻掩模的方法,其包括(1)在衬底上形成抗蚀剂层; (2)将抗蚀剂层的一个或多个区域暴露于能量源,以便改变暴露区域的物理性质和化学性质中的至少一个; (3)对抗蚀剂层进行硬化处理以提高抗蚀剂层相对于抗蚀剂层的第二区域的第一区域的耐蚀刻性,硬化过程包括将抗蚀剂层暴露于原子层内的一个或多个反应性物质 沉积(ALD)室; 和(4)干蚀刻抗蚀剂层以除去一个或多个第二区域并在抗蚀剂层中形成图案。 提供其他实施例。

    Lateral oxidation process flows
    43.
    发明授权
    Lateral oxidation process flows 有权
    横向氧化工艺流程

    公开(公告)号:US09343309B1

    公开(公告)日:2016-05-17

    申请号:US14657693

    申请日:2015-03-13

    Abstract: Methods of laterally oxidizing features of a patterned substrate are described. A capping layer may be disposed above lateral features to laterally confine the oxidation. The oxidizable features may be material patterned near the optical resolution of a photolithography system using a high-resolution photomask. The oxidizable features may be wider than the spaces between the oxidizable features and may be about three times the width of the spaces. Oxidized portions may be formed on either side of repeated oxidizable features. The unoxidized portions may then be removed as part of a self-aligned double patterning (SADP) process. A gapfill layer deposited thereon may be etched or polished back to form alternating fill and non-sacrificial features.

    Abstract translation: 描述了图案化衬底的横向氧化特征的方法。 覆盖层可以设置在横向特征上方以横向限制氧化。 可氧化特征可以是使用高分辨率光掩模的光刻系统的光学分辨率附近的材料图案。 可氧化特征可以比可氧化特征之间的空间宽,并且可以是空间宽度的大约三倍。 可以在重复的可氧化特征的任一侧上形成氧化部分。 然后可以将非氧化部分作为自对准双重图案化(SADP)工艺的一部分移除。 可以将沉积在其上的间隙填充层进行蚀刻或抛光以形成交替的填充和非牺牲特征。

    RESIST HARDENING AND DEVELOPMENT PROCESSES FOR SEMICONDUCTOR DEVICE MANUFACTURING
    45.
    发明申请
    RESIST HARDENING AND DEVELOPMENT PROCESSES FOR SEMICONDUCTOR DEVICE MANUFACTURING 有权
    用于半导体器件制造的耐腐蚀和开发工艺

    公开(公告)号:US20140263172A1

    公开(公告)日:2014-09-18

    申请号:US14205324

    申请日:2014-03-11

    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

    Abstract translation: 在一些实施例中,提供了在衬底上形成蚀刻掩模的方法,其包括(1)在衬底上形成抗蚀剂层; (2)将抗蚀剂层的一个或多个区域暴露于能量源,以便改变暴露区域的物理性质和化学性质中的至少一个; (3)对抗蚀剂层进行硬化处理以提高抗蚀剂层相对于抗蚀剂层的第二区域的第一区域的耐蚀刻性,硬化过程包括将抗蚀剂层暴露于原子层内的一个或多个反应性物质 沉积(ALD)室; 和(4)干蚀刻抗蚀剂层以除去一个或多个第二区域并在抗蚀剂层中形成图案。 提供其他实施例。

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