公开(公告)号：US20120068174A1

公开(公告)日：2012-03-22

申请号：US12886612

申请日：2010-09-21

Applicant: Arvind Kumar ,  Anthony I-Chih Chou ,  Shreesh Narasimha

Inventor： Arvind Kumar ,  Anthony I-Chih Chou ,  Shreesh Narasimha

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.

Abstract translation: 公开了一种用于电气掩模检查的装置和方法。 在两个金属层和通孔层之间形成扫描链。 三层之一是被测功能层，另外两层是测试层。 使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。

公开(公告)号：US08034692B2

公开(公告)日：2011-10-11

申请号：US12581924

申请日：2009-10-20

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US20110163383A1

公开(公告)日：2011-07-07

申请号：US12683456

申请日：2010-01-07

Applicant: Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC: H01L27/12 ,  H01L21/86

CPC classification number: H01L27/1207 ,  H01L21/84

Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

Abstract translation: 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US07936042B2

公开(公告)日：2011-05-03

申请号：US11939017

申请日：2007-11-13

Applicant: Arvind Kumar

Inventor： Arvind Kumar

IPC: H01L29/02

CPC classification number: H01L21/26586 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.

Abstract translation: 提供了包括硅含量体的场效应晶体管。 在形成栅极电介质，栅极电极和第一栅极间隔物之后，形成漏极侧沟槽并填充宽带隙半导体材料。 可选地，可以形成源极沟槽并填充硅锗合金以增强场效应晶体管的导通电流。 进行光晕注入和源极和漏极离子注入以形成各种掺杂区域。 由于宽带隙半导体材料作为比硅的带隙宽的带隙，由于在漏极中使用宽带隙半导体材料，因此冲击电离降低，因此，场效应晶体管的击穿电压比较 涉及在漏极区域中使用硅的晶体管。

公开(公告)号：US07838942B2

公开(公告)日：2010-11-23

申请号：US12144272

申请日：2008-06-23

Applicant: Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

Inventor： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

IPC: H01L29/76

CPC classification number: H01L27/1108

Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

Abstract translation: 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

公开(公告)号：US20100249175A1

公开(公告)日：2010-09-30

申请号：US11478453

申请日：2006-06-29

Applicant: W. David Wilson ,  David W. Boykin ,  Elizabeth W. White ,  Mohamed A. Ismail ,  Arvind Kumar ,  Rupesh Nanjunda ,  Richard R. Tidwell

Inventor： W. David Wilson ,  David W. Boykin ,  Elizabeth W. White ,  Mohamed A. Ismail ,  Arvind Kumar ,  Rupesh Nanjunda ,  Richard R. Tidwell

IPC: A61K31/437 ,  C12P19/34 ,  C12N5/071 ,  C12N5/02 ,  A61K31/4178 ,  C07H21/04 ,  C07D471/04 ,  C07D405/14 ,  A61P35/04

CPC classification number: A61K31/341 ,  A61K31/33 ,  A61K31/381 ,  A61K31/4164 ,  A61K31/4184 ,  A61K31/443 ,  C07D345/00 ,  C07D405/14 ,  C07D421/14 ,  Y02A50/409 ,  Y02A50/411 ,  Y02A50/415

Abstract: Dicationic compounds that are highly selective for binding G-quadruplex DNA are described. Several compounds exhibit groove binding toward G-quadruplex DNA and in vitro and in vivo activity versus Trypanosoma brucei rhodesiense. The compounds represent novel drugs for the treatment of cancer, malaria, leishmania, and trypanosomiasis.

Abstract translation: 描述了对结合G-四链体DNA具有高度选择性的起始化合物。 几种化合物表现出与G-四链体DNA结合的凹槽，并且与罗氏黑曲霉相比体外和体内活性。 这些化合物代表用于治疗癌症，疟疾，利什曼原虫和锥虫病的新型药物。

公开(公告)号：US20090172438A1

公开(公告)日：2009-07-02

申请号：US11964439

申请日：2007-12-26

Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

公开(公告)号：US07536479B2

公开(公告)日：2009-05-19

申请号：US10985123

申请日：2004-11-09

Applicant: Ravi Sahita ,  Priya Rajagopal ,  David Durham ,  Scott Hahn ,  Carey Smith ,  Arvind Kumar

Inventor： Ravi Sahita ,  Priya Rajagopal ,  David Durham ,  Scott Hahn ,  Carey Smith ,  Arvind Kumar

IPC: G06F15/16

CPC classification number: H04L29/12009 ,  H04L29/12405 ,  H04L61/2528

Abstract: In one embodiment, a method is provided. The method of this embodiment provides receiving one or more packets that are addressed to an alternate IP (Internet Protocol) address and that include a LADLC (local application data link control) address in a system having an operating system-independent processor (“service processor”) associated with the alternate IP address and an alternate DLC address, and an embedded network stack (“ENS”) of the service processor associated with a primary IP address; performing filtering to determine if the LADLC address matches the alternate DLC address; and if the LADLC address matches the alternate DLC address, then replacing the alternate IP address of the one or more packets with the primary IP address, and forwarding the one or more packets to the ENS.

Abstract translation: 在一个实施例中，提供了一种方法。 该实施例的方法提供接收一个或多个寻址到备用IP（因特网协议）地址的分组，并且在具有与操作系统无关的处理器（“服务处理器”）的系统中包括LADLC（本地应用数据链路控制）地址 “）与备用IP地址和备用DLC地址相关联，以及与主IP地址相关联的服务处理器的嵌入式网络堆栈（”ENS“）; 执行滤波以确定LADLC地址是否与备用DLC地址匹配; 并且如果LADLC地址与备用DLC地址匹配，则用主IP地址替换一个或多个数据包的备用IP地址，并将一个或多个数据包转发到ENS。

公开(公告)号：US07418608B2

公开(公告)日：2008-08-26

申请号：US10871587

申请日：2004-06-17

Applicant: Arvind Kumar ,  David J. O'Shea

Inventor： Arvind Kumar ,  David J. O'Shea

IPC: G06F1/26

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/171

Abstract: A method and an apparatus for managing power consumption of a server have been disclosed. In one embodiment, the method includes allowing a user to set a power management policy on a server, monitoring power consumption of a plurality of blades in the server, and automatically managing power consumption of the server in response to the power consumption of the plurality of blades based on the power management policy set by the user. Other embodiments have been claimed and described.

Abstract translation: 已经公开了一种用于管理服务器的功耗的方法和装置。 在一个实施例中，该方法包括允许用户在服务器上设置电源管理策略，监视服务器中的多个刀片的功耗，以及响应于多个服务器的功耗而自动管理服务器的功耗 基于用户设置的电源管理策略。 已经要求和描述了其它实施例。

公开(公告)号：US20080155092A1

公开(公告)日：2008-06-26

申请号：US11644703

申请日：2006-12-22

Applicant: Arvind Kumar ,  Alok Prakash ,  Sushil Patel

Inventor： Arvind Kumar ,  Alok Prakash ,  Sushil Patel

IPC: G06F9/46 ,  G06F15/173

CPC classification number: G06F11/348 ,  G06F11/3409 ,  G06F11/3476 ,  G06F21/10 ,  G06F2201/88 ,  G06F2221/2135 ,  H04L43/04 ,  H04L43/0817

Abstract: A method, apparatus and system for securely metering resource usage on a computing platform. Specifically, in one embodiment, various hardware metering counters on the device may provide a secure processing partition with usage information to enable the resources to be metered within the secure partition.

Abstract translation: 一种用于在计算平台上安全地计量资源使用的方法，装置和系统。 具体地，在一个实施例中，设备上的各种硬件计费计数器可以提供具有使用信息的安全处理分区，以使能够在安全分区内计量资源。