公开(公告)号：US07728336B2

公开(公告)日：2010-06-01

申请号：US12310992

申请日：2007-09-13

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda ,  Makoto Kato

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda ,  Makoto Kato

IPC分类号： H01L31/0312

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

摘要翻译： 在包括在低浓度p型沉积膜中通过离子注入形成的沟道区和n型反向电子引导路径的SiC垂直MOSFET中，由于注入掩模定位失败，沟道区的宽度可能部分变窄， 并且器件的耐压可能降低，因此器件几乎不能满足低导通电阻和高耐压两者。 在本发明中，第二倒置层（41,42）从反转层（40）的左右两侧设置为相同距离，作为装置中的电子引导路径，反相层通过同时离子 使用相同的掩模进行注入，因此，将器件中的所有沟道区域的长度均匀化，从而解决问题。

公开(公告)号：US20090321746A1

公开(公告)日：2009-12-31

申请号：US12310024

申请日：2007-08-01

申请人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

发明人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

IPC分类号： H01L29/24 ,  H01L21/28

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  Y10S438/931

摘要： A low on-resistance silicon carbide semiconductor device is provided that includes an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide.The silicon carbide semiconductor device includes: at least an insulating film 7, formed on an upper surface of silicon carbide; and at least an ohmic electrode 12, formed of an alloy comprising nickel and titanium, or a silicide comprising nickel and titanium, and which is formed on the lower surface of the silicon carbide.

摘要翻译： 提供一种低导通电阻碳化硅半导体器件，其包括形成在碳化硅的下表面上的低接触电阻和高粘合强度的欧姆电极。 所述碳化硅半导体器件包括：至少形成在碳化硅的上表面上的绝缘膜7; 以及至少一个由包含镍和钛的合金形成的欧姆电极12或者包含镍和钛的硅化物，并且形成在碳化硅的下表面上。

公开(公告)号：US20090134402A1

公开(公告)日：2009-05-28

申请号：US11718036

申请日：2005-09-30

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Mitsuo Okamoto ,  Kenji Fukuda

IPC分类号： H01L29/78 ,  H01L21/3205 ,  H01L21/02

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7828

摘要： In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.

摘要翻译： 在具有在其中设置有沟道区域的低浓度p型沉积膜和由n型通过离子注入的反向注入产生的基极区域的SiC垂直MOSFET中，用于当时发生的栅极氧化膜的介电击穿 关闭，从而防止进一步的阻塞电压增强。 通过在低浓度p型沉积膜和高浓度栅极层之间插入低浓度n型沉积膜并且将由反向注入产生的碱性区域选择性地形成为n型，已经解决了该问题 通过离子注入低浓度p型沉积膜，使得高浓度栅极层与沟道区域和栅极氧化物层之间的沉积膜的厚度增加。

公开(公告)号：US06750477B2

公开(公告)日：2004-06-15

申请号：US10121623

申请日：2002-04-15

申请人： Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Hidekatsu Onose ,  Saburo Oikawa

发明人： Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Hidekatsu Onose ,  Saburo Oikawa

IPC分类号： H01L310312

CPC分类号： H01L29/7722 ,  H01L29/1608

摘要： In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by the first gate layer (4), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.

摘要翻译： 在静电感应晶体管中，除了第一栅极层（4）之外，还具有与第一栅极层（4）相比具有较浅深度和间隔更窄的多个第二栅极层（41） 由第一栅极层（4）包围，从而实现具有优异的截止特性的SiC静态感应晶体管，同时确保其制造期间所需的加工精度。

公开(公告)号：US06566726B1

公开(公告)日：2003-05-20

申请号：US09516501

申请日：2000-03-01

申请人： Hidekatsu Onose ,  Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Saburou Oikawa

发明人： Hidekatsu Onose ,  Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Saburou Oikawa

IPC分类号： H01L2940

CPC分类号： H01L29/0615 ,  H02M7/003

摘要： To reduce the field intensity on the termination surface, almost not affecting the on-characteristic, a drift layer is made of two layers, an n-layer and n− layer, and a termination region is formed on the surface of the above n− layer. An impurity concentration ratio between the n− layer and the n-layer is less than 1:2, and the thickness of the n− layer is less than that of a source n+ layer. Reliability can be secured even in a high temperature operation.

摘要翻译： 为了降低终端表面上的场强，几乎不影响导通特性，漂移层由n层和n层两层构成，并且在上述n-层的表面上形成端接区， 层。 n层和n层之间的杂质浓度比小于1：2，n层的厚度小于源n +层的厚度。 即使在高温操作中也可以确保可靠性。

公开(公告)号：US06384428B1

公开(公告)日：2002-05-07

申请号：US09646305

申请日：2000-09-15

申请人： Toshiyuki Oono ,  Takayuki Iwasaki ,  Tsutomu Yatsuo

发明人： Toshiyuki Oono ,  Takayuki Iwasaki ,  Tsutomu Yatsuo

IPC分类号： H01L310312

CPC分类号： H01L29/7395 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068

摘要： The present semiconductor switching device comprises a silicon carbide single crystal of hexagonal symmetry having a first conductive type and a semiconductor region of a second conductive type opposite to the first conductive type and locating in the silicon carbide single crystal. The silicon carbide single crystal of the first conductive type and the semiconductor region of the seconductive type form a pn junction. The pn junction interface has an interface extended in the depth direction from the surface of the silicon carbide single crystal, and the interface includes a crystal plane in parallel to the orientation of the silicon carbide single crystal or approximately in parallel thereto, thereby reducing the leak current.

摘要翻译： 本半导体开关器件包括具有第一导电类型的六边形对称的碳化硅单晶和与第一导电类型相反并且位于碳化硅单晶中的第二导电类型的半导体区域。 第一导电类型的碳化硅单晶和第二导电类型的半导体区域形成pn结。 pn结界面具有从碳化硅单晶的表面沿深度方向延伸的界面，并且界面包括平行于碳化硅单晶的<1120>取向的晶体平面，或者大致与其平行。 减少漏电流。

公开(公告)号：US06169672A

公开(公告)日：2001-01-02

申请号：US09202924

申请日：1998-12-23

申请人： Shin Kimura ,  Tsutomu Yatsuo ,  Takayuki Iwasaki

发明人： Shin Kimura ,  Tsutomu Yatsuo ,  Takayuki Iwasaki

IPC分类号： H02H7122

CPC分类号： H02M1/34 ,  H02M7/519 ,  H02M2001/344 ,  H02M2001/346 ,  H03K17/08144 ,  Y02B70/1483 ,  Y02B70/1491

摘要： A power converting apparatus comprising a group of semiconductor switches and DC terminals electrically connected to the group of semiconductor switches, in which a clamping circuit is connected to the semiconductor switches or the DC terminals. Otherwise, a diode having a wide band gap is connected in parallel with a snubber diode or a snubber capacitor of a snubber circuit connected in parallel with the semiconductor switches. With such arrangement, an overvoltage or oscillating voltage impressed on the semiconductor switches is suppressed.

摘要翻译： 一种电力转换装置，包括电连接到半导体开关组的半导体开关和DC端子组，其中钳位电路连接到半导体开关或DC端子。 否则，具有宽带隙的二极管与与半导体开关并联连接的缓冲电路的缓冲二极管或缓冲电容器并联连接。 通过这种布置，抑制了对半导体开关施加的过电压或振荡电压。

公开(公告)号：US4691223A

公开(公告)日：1987-09-01

申请号：US795464

申请日：1985-11-06

申请人： Susumu Murakami ,  Teruyuki Kagami ,  Tsutomu Yatsuo ,  Masaaki Takahashi

发明人： Susumu Murakami ,  Teruyuki Kagami ,  Tsutomu Yatsuo ,  Masaaki Takahashi

IPC分类号： H01L29/73 ,  H01L21/314 ,  H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/732 ,  H01L29/74 ,  H01L27/02

CPC分类号： H01L29/405 ,  Y10S257/905

摘要： A semiconductor device includes a semiconductor substrate having at least three semiconductor layers of alternately different conductivity types between a pair of principal surfaces. A pair of main electrodes are kept in low-resistance contact with the outermost ones of the semiconductor layers. A surface-passivation insulating film is provided on an exposed surface of the semiconductor substrate. A resistive material sheet is provided on the insulating film and connected electrically to semiconductor layers having their potentials substantially equal to the main electrodes.

摘要翻译： 半导体器件包括在一对主表面之间具有交替不同导电类型的至少三个半导体层的半导体衬底。 一对主电极与最外面的半导体层保持低电阻接触。 表面钝化绝缘膜设置在半导体衬底的暴露表面上。 电阻材料片设置在绝缘膜上并与其电位基本上等于主电极的半导体层电连接。

公开(公告)号：US3947864A

公开(公告)日：1976-03-30

申请号：US439717

申请日：1974-02-05

申请人： Tsutomu Yatsuo ,  Tatsuya Kamei ,  Koichi Wajima

发明人： Tsutomu Yatsuo ,  Tatsuya Kamei ,  Koichi Wajima

IPC分类号： H01L21/322 ,  H01L29/74 ,  H01L29/747

CPC分类号： H01L29/7416

摘要： A diode-integrated thyristor comprising a region having a function of a thyristor and a region having a function of a diode which are integrated in the same semiconductor substrate and whose rectifying directions are opposite to each other, the carriers in the region having the function of a diode having a longer life time than the carriers in the region having the function of a thyristor.

摘要翻译： 一种二极管集成晶闸管，包括具有晶闸管功能的区域和具有集成在同一半导体衬底中并且其整流方向彼此相反的二极管功能的区域，具有功能的区域中的载流子 具有比具有晶闸管功能的区域中的载流子寿命更长的二极管。