公开(公告)号：US3947864A

公开(公告)日：1976-03-30

申请号：US439717

申请日：1974-02-05

申请人： Tsutomu Yatsuo ,  Tatsuya Kamei ,  Koichi Wajima

发明人： Tsutomu Yatsuo ,  Tatsuya Kamei ,  Koichi Wajima

IPC分类号： H01L21/322 ,  H01L29/74 ,  H01L29/747

CPC分类号： H01L29/7416

摘要： A diode-integrated thyristor comprising a region having a function of a thyristor and a region having a function of a diode which are integrated in the same semiconductor substrate and whose rectifying directions are opposite to each other, the carriers in the region having the function of a diode having a longer life time than the carriers in the region having the function of a thyristor.

摘要翻译： 一种二极管集成晶闸管，包括具有晶闸管功能的区域和具有集成在同一半导体衬底中并且其整流方向彼此相反的二极管功能的区域，具有功能的区域中的载流子 具有比具有晶闸管功能的区域中的载流子寿命更长的二极管。

公开(公告)号：US3967308A

公开(公告)日：1976-06-29

申请号：US451679

申请日：1974-03-15

申请人： Tsutomu Yatsuo ,  Tatsuya Kamei ,  Takuzo Ogawa ,  Tomoyuki Tanaka

发明人： Tsutomu Yatsuo ,  Tatsuya Kamei ,  Takuzo Ogawa ,  Tomoyuki Tanaka

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/74 ,  H01L29/747

CPC分类号： H01L29/747 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/42308 ,  H01L29/74

摘要： A thyristor with a gate electrode formed on the side of an anode electrode. An auxiliary region of a large lateral resistance is formed in a surface layer of the substrate between the anode and gate electrodes.

摘要翻译： 具有形成在阳极侧的栅电极的晶闸管。 在阳极和栅电极之间的衬底的表面层中形成有大的横向电阻的辅助区域。

公开(公告)号：US3943550A

公开(公告)日：1976-03-09

申请号：US534373

申请日：1974-12-19

申请人： Nobutake Konishi ,  Tsutomu Yatsuo ,  Tatsuya Kamei ,  Masahiro Okamura ,  Takuzo Ogawa

发明人： Nobutake Konishi ,  Tsutomu Yatsuo ,  Tatsuya Kamei ,  Masahiro Okamura ,  Takuzo Ogawa

IPC分类号： H01L31/111 ,  H01L29/74

CPC分类号： H01L31/1113

摘要： A light-activated semiconductor-controlled rectifier device comprising four layers of PNPN is disclosed in which a part of the edges of the PN junction formed between the intermediate P-type layer and the intermediate N-type layer is exposed on the same side on which the outer P-type layer is exposed, so that a photo-trigger signal is radiated on that exposed part of the edges of the PN junction.

摘要翻译： 公开了一种包括四层PNPN的光激活半导体控制整流器件，其中形成在中间P型层和中间N型层之间的PN结的边缘的一部分暴露在同一侧上， 暴露外部P型层，使得在PN结的边缘的暴露部分上照射触发信号。

公开(公告)号：US4016593A

公开(公告)日：1977-04-05

申请号：US583406

申请日：1975-06-03

申请人： Nobutake Konishi ,  Tsutomu Yatsuo ,  Tatsuya Kamei ,  Masahiro Okamura ,  Takuzo Ogawa

发明人： Nobutake Konishi ,  Tsutomu Yatsuo ,  Tatsuya Kamei ,  Masahiro Okamura ,  Takuzo Ogawa

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L31/0203 ,  H01L31/111

CPC分类号： H01L31/0203 ,  H01L31/1113

摘要： A bidirectional photothyristor device comprises a semiconductive substrate including an NPNPN quintuple layer in which projections of both the outer layers Ns in the stacking direction are not overlapped so as to define two quadruple layer regions each having either one of the outer layers Ns as an end layer, a pair of main electrodes connecting the two quadruple layer regions in parallel relationship, a recess formed between the two quadruple layer regions within the semiconductive substrate and to which two intermediate P-N junctions are exposed, and means for applying a light trigger signal to the recess.

摘要翻译： 双向光闸晶体管装置包括一个包括NPNPN五元组的半导体衬底，其中层叠方向上的两个外层Ns的突起不重叠，以便限定两个四层层，每层具有外层Ns中的任一层作为端层 一对主电极并联连接两个四重层区域，形成在半导体衬底内的两个四重层区域之间并且两个中间PN结露出的凹部和用于将光触发信号施加到凹部的装置 。

公开(公告)号：US20090173949A1

公开(公告)日：2009-07-09

申请号：US12281391

申请日：2006-12-27

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L21/8213 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7806

摘要： This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

摘要翻译： 本发明具有一个电池，该电池结合了内置的肖特基二极管区域，该区域设置在构成在具有沟道区域和基极区域的低密度p型沉积膜中提供的SiC垂直MOSFET的基本单元的至少一部分中 n型离子注入。 该内置的肖特基二极管区域内置有低导通电阻的肖特基二极管，该二极管由设置在高密度栅极层中的第二缺陷盘形成，第二n型基极层穿透低密度p型 沉积层形成在其上，到达第二缺陷部分的n型漂移层，并且由于p型沉积层通过从n型杂质离子注入n型杂质而转变为n型，从而形成其自身的形成 表面以及以与第二n型基底层的表面暴露部分形成肖特基势垒的方式连接的源电极。

公开(公告)号：US20090072244A1

公开(公告)日：2009-03-19

申请号：US12281902

申请日：2007-01-16

申请人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

发明人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

IPC分类号： H01L29/24 ,  H01L21/44

CPC分类号： H01L21/31658 ,  H01L21/02126 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/324 ,  Y10S438/931

摘要： The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

摘要翻译： 本发明的目的是提供一种用于制造半导体器件的方法，该半导体器件为了形成这种欧姆接触的目的而进行了退火处理，以能够降低欧姆接触电阻并且提供在碳化硅的（000-1）面上， 绝缘膜并提供半导体器件。 制造碳化硅半导体器件的方法包括以下步骤：在至少包含氧和水分的气体中在碳化硅半导体的（000-1）面上进行热氧化，从而以这种方式形成绝缘膜 为了接触碳化硅半导体的（000-1）面，除去绝缘膜的一部分，从而在其中形成开口部，在开口部的至少一部分上沉积接触金属，进行热处理，从而形成 接触金属和碳化硅的反应层，其中热处理在惰性气体和氢气的混合气体中实施。

公开(公告)号：US20080203400A1

公开(公告)日：2008-08-28

申请号：US12025445

申请日：2008-02-04

申请人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

发明人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

IPC分类号： H01L29/161

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7835

摘要： A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

摘要翻译： 提供半导体器件和使用（000-1）面的碳化硅衬底的器件的制造方法。 通过优化栅极氧化后使用的热处理方法来制造具有高阻断电压和高沟道迁移率的SiC半导体器件。 制造半导体器件的方法包括以下步骤：在由具有（000-1）面取向的碳化硅形成的半导体区上形成栅极绝缘层，在栅极绝缘层上形成栅电极，在半导体上形成电极 区域，清洁半导体区域表面。 在800℃至1150℃的温度下，在含有1％或更多的H 2 O（水）蒸气的气氛中形成栅极绝缘层，以降低界面陷阱密度 栅极绝缘层和半导体区域之间的界面。

公开(公告)号：US20060057796A1

公开(公告)日：2006-03-16

申请号：US10531582

申请日：2003-10-03

申请人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi

发明人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi

IPC分类号： H01L21/8238

CPC分类号： H01L29/66477 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802

摘要： A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

摘要翻译： 具有低导通电阻和高阻断电压的碳化硅垂直MOSFET。 在第一导电类型的高浓度碳化硅衬底的表面上形成第一导电类型的低浓度碳化硅的第一沉积膜。 形成在第一沉积膜上的是第二沉积膜，其包括第二导电类型的高浓度栅极区域，其中第一区域被选择性地去除。 在第二沉积膜上形成第三沉积膜，其包括比选择性去除的第一区域宽的第二区域，第一导电类型的高浓度源区域和第二导电类型的低浓度栅极区域。 第一导电类型的低浓度基区形成为与第一和第二区域中的第一沉积膜接触。

公开(公告)号：US06180959B2

公开(公告)日：2001-01-30

申请号：US09061145

申请日：1998-04-16

申请人： Takayuki Iwasaki ,  Toshiyuki Ohno ,  Tsutomu Yatsuo

发明人： Takayuki Iwasaki ,  Toshiyuki Ohno ,  Tsutomu Yatsuo

IPC分类号： H01L29161

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/7392 ,  H01L29/7722 ,  H03K17/687

摘要： In a silicon carbide static induction transistor, at a surface part of a semiconductor substrate, a p-type gate region is formed partially overlapping a n-type source region, whereby the high accuracy in alignment between the gate region and the source region is not required, and the gate withstand voltage can be highly increased since the substrate is made of silicon carbide, which improves the yield of static induction transistors.

摘要翻译： 在碳化硅静电感应晶体管中，在半导体衬底的表面部分，形成与n型源极区域部分重叠的p型栅极区域，由此栅极区域与源极区域之间的高精度对准 并且栅极耐受电压可以高度增加，因为衬底由碳化硅制成，这提高了静电感应晶体管的产量。

公开(公告)号：US4626888A

公开(公告)日：1986-12-02

申请号：US550586

申请日：1983-11-10

申请人： Takahiro Nagano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Akira Horie

发明人： Takahiro Nagano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Akira Horie

IPC分类号： H01L29/423 ,  H01L29/74 ,  H01L29/744 ,  H01L23/48

CPC分类号： H01L29/42308 ,  H01L29/74 ,  H01L29/744

摘要： In accordance with the present invention, a plurality of strip-shaped emitter layers on the cathode side are radially arranged on one main surface of the semiconductor substrate while forming a plurality of rings. A gate electrode is in ohmic contact with a part of a base layer which surrounds and is adjacent to each of said emitter layers on the cathode side. Between rings formed by said emitter layers on the cathode side, a ring-shaped gate collecting electrode is provided to be connected to said gate electrode. The gate collecting electrode is provided at a position to balance the potential differences produced by gate currents respectively corresponding to inside and outside of said gate collecting electrode.

摘要翻译： 根据本发明，阴极侧的多个条状发射极层径向地布置在半导体衬底的一个主表面上，同时形成多个环。 栅电极与基极层的一部分欧姆接触，该基极层围绕并邻近阴极侧的每个发射极层。 在由阴极侧上的发射极层形成的环之间，设置有环形栅极集电极，以连接到所述栅电极。 栅极集电极设置在平衡由分别对应于所述栅极集电极的内部和外部的栅极电流产生的电位差的位置。