公开(公告)号：US06566726B1

公开(公告)日：2003-05-20

申请号：US09516501

申请日：2000-03-01

申请人： Hidekatsu Onose ,  Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Saburou Oikawa

发明人： Hidekatsu Onose ,  Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Saburou Oikawa

IPC分类号： H01L2940

CPC分类号： H01L29/0615 ,  H02M7/003

摘要： To reduce the field intensity on the termination surface, almost not affecting the on-characteristic, a drift layer is made of two layers, an n-layer and n− layer, and a termination region is formed on the surface of the above n− layer. An impurity concentration ratio between the n− layer and the n-layer is less than 1:2, and the thickness of the n− layer is less than that of a source n+ layer. Reliability can be secured even in a high temperature operation.

摘要翻译： 为了降低终端表面上的场强，几乎不影响导通特性，漂移层由n层和n层两层构成，并且在上述n-层的表面上形成端接区， 层。 n层和n层之间的杂质浓度比小于1：2，n层的厚度小于源n +层的厚度。 即使在高温操作中也可以确保可靠性。

公开(公告)号：US06750477B2

公开(公告)日：2004-06-15

申请号：US10121623

申请日：2002-04-15

申请人： Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Hidekatsu Onose ,  Saburo Oikawa

发明人： Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Hidekatsu Onose ,  Saburo Oikawa

IPC分类号： H01L310312

CPC分类号： H01L29/7722 ,  H01L29/1608

摘要： In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by the first gate layer (4), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.

摘要翻译： 在静电感应晶体管中，除了第一栅极层（4）之外，还具有与第一栅极层（4）相比具有较浅深度和间隔更窄的多个第二栅极层（41） 由第一栅极层（4）包围，从而实现具有优异的截止特性的SiC静态感应晶体管，同时确保其制造期间所需的加工精度。

公开(公告)号：US20050006649A1

公开(公告)日：2005-01-13

申请号：US10824442

申请日：2004-04-15

申请人： Takayuki Iwasaki ,  Tsutomu Yatsuo ,  Hidekatsu Onose ,  Toshiyuki Oono

发明人： Takayuki Iwasaki ,  Tsutomu Yatsuo ,  Hidekatsu Onose ,  Toshiyuki Oono

IPC分类号： H01L29/772 ,  H02M7/00 ,  H01L31/0312

CPC分类号： H02M7/003 ,  H01L29/7722

摘要： A static induction transistor includes a semiconductor substrate with an energy band gap greater than that of silicon, and the semiconductor substrate has a first gate region to which a gate electrode is connected; and a second gate region positioned within a first semiconductor region which becomes a drain region, and the first gate region is in contact with a second semiconductor region which becomes a source region. According to this construction, the OFF characteristics of the static induction transistor are improved.

摘要翻译： 静电感应晶体管包括具有比硅的能带隙大的能带隙的半导体衬底，并且半导体衬底具有连接有栅电极的第一栅极区域; 以及位于成为漏极区域的第一半导体区域内的第二栅极区域，并且第一栅极区域与成为源极区域的第二半导体区域接触。 根据该结构，能够提高静电感应晶体管的OFF特性。

公开(公告)号：US06353236B1

公开(公告)日：2002-03-05

申请号：US09396733

申请日：1999-09-15

申请人： Tsutomu Yatsuo ,  Takayuki Iwasaki ,  Hidekatsu Onose ,  Shin Kimura

发明人： Tsutomu Yatsuo ,  Takayuki Iwasaki ,  Hidekatsu Onose ,  Shin Kimura

IPC分类号： H01L310312

CPC分类号： H01C7/10 ,  H01C7/12 ,  H01L29/8605 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49431

摘要： A wide bandgap semiconductor single crystal is applied as a semiconductor substrate material of a semiconductor surge absorber, and a surge absorption operation starting voltage is set by a punchthrough of a pn junction, to obtain a semiconductor surge absorber with a repetitive operation and a high surge endurance.

摘要翻译： 应用宽带隙半导体单晶作为半导体浪涌吸收体的半导体衬底材料，通过pn结穿透来设置浪涌吸收操作启动电压，以获得具有重复操作和高浪涌的半导体浪涌吸收器 耐力。

公开(公告)号：US06180959B2

公开(公告)日：2001-01-30

申请号：US09061145

申请日：1998-04-16

申请人： Takayuki Iwasaki ,  Toshiyuki Ohno ,  Tsutomu Yatsuo

发明人： Takayuki Iwasaki ,  Toshiyuki Ohno ,  Tsutomu Yatsuo

IPC分类号： H01L29161

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/7392 ,  H01L29/7722 ,  H03K17/687

摘要： In a silicon carbide static induction transistor, at a surface part of a semiconductor substrate, a p-type gate region is formed partially overlapping a n-type source region, whereby the high accuracy in alignment between the gate region and the source region is not required, and the gate withstand voltage can be highly increased since the substrate is made of silicon carbide, which improves the yield of static induction transistors.

摘要翻译： 在碳化硅静电感应晶体管中，在半导体衬底的表面部分，形成与n型源极区域部分重叠的p型栅极区域，由此栅极区域与源极区域之间的高精度对准 并且栅极耐受电压可以高度增加，因为衬底由碳化硅制成，这提高了静电感应晶体管的产量。

公开(公告)号：US5736753A

公开(公告)日：1998-04-07

申请号：US521548

申请日：1995-08-30

申请人： Toshiyuki Ohno ,  Yohsuke Inoue ,  Daisuke Kawase ,  Yuzo Kozono ,  Takaya Suzuki ,  Tsutomu Yatsuo

发明人： Toshiyuki Ohno ,  Yohsuke Inoue ,  Daisuke Kawase ,  Yuzo Kozono ,  Takaya Suzuki ,  Tsutomu Yatsuo

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/78 ,  H01L29/808 ,  H01L31/0312 ,  H01L29/74 ,  H01L29/861

CPC分类号： H01L29/7802 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7801 ,  H01L29/7813 ,  H01L29/8083

摘要： To provide a field-effect transistor having a large power conversion capacity and its fabrication method by decreasing the leakage current between the source and the drain of a semiconductor device made of hexagonal-system silicon carbide when the gate voltage of the semiconductor device is turned off and also decreasing the electrical resistance of the semiconductor device when the gate voltage of the semiconductor device is turned on. The main current path of the field-effect transistor is formed so that the current flowing between the source and the drain of, for example, a field-effect transistor flows in the direction parallel with the {0001} plane and a channel forming plane is parallel with the {1120} plane. �Selected Drawing!FIG. 1

摘要翻译： 为了提供具有大的功率转换能力的场效应晶体管及其制造方法，当半导体器件的栅极电压被关断时，通过减小由六方晶系碳化硅制成的半导体器件的源极和漏极之间的漏电流 并且当半导体器件的栅极电压导通时也降低半导体器件的电阻。 形成场效应晶体管的主电流路径，使得在例如场效应晶体管的源极和漏极之间流动的电流沿与{0001}平面平行的方向流动，沟道形成面为 与{1120}平面平行。 [所选图]

公开(公告)号：US20090173949A1

公开(公告)日：2009-07-09

申请号：US12281391

申请日：2006-12-27

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L21/8213 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7806

摘要： This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

摘要翻译： 本发明具有一个电池，该电池结合了内置的肖特基二极管区域，该区域设置在构成在具有沟道区域和基极区域的低密度p型沉积膜中提供的SiC垂直MOSFET的基本单元的至少一部分中 n型离子注入。 该内置的肖特基二极管区域内置有低导通电阻的肖特基二极管，该二极管由设置在高密度栅极层中的第二缺陷盘形成，第二n型基极层穿透低密度p型 沉积层形成在其上，到达第二缺陷部分的n型漂移层，并且由于p型沉积层通过从n型杂质离子注入n型杂质而转变为n型，从而形成其自身的形成 表面以及以与第二n型基底层的表面暴露部分形成肖特基势垒的方式连接的源电极。

公开(公告)号：US20090072244A1

公开(公告)日：2009-03-19

申请号：US12281902

申请日：2007-01-16

申请人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

发明人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

IPC分类号： H01L29/24 ,  H01L21/44

CPC分类号： H01L21/31658 ,  H01L21/02126 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/324 ,  Y10S438/931

摘要： The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

摘要翻译： 本发明的目的是提供一种用于制造半导体器件的方法，该半导体器件为了形成这种欧姆接触的目的而进行了退火处理，以能够降低欧姆接触电阻并且提供在碳化硅的（000-1）面上， 绝缘膜并提供半导体器件。 制造碳化硅半导体器件的方法包括以下步骤：在至少包含氧和水分的气体中在碳化硅半导体的（000-1）面上进行热氧化，从而以这种方式形成绝缘膜 为了接触碳化硅半导体的（000-1）面，除去绝缘膜的一部分，从而在其中形成开口部，在开口部的至少一部分上沉积接触金属，进行热处理，从而形成 接触金属和碳化硅的反应层，其中热处理在惰性气体和氢气的混合气体中实施。

公开(公告)号：US20080203400A1

公开(公告)日：2008-08-28

申请号：US12025445

申请日：2008-02-04

申请人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

发明人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

IPC分类号： H01L29/161

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7835

摘要： A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

摘要翻译： 提供半导体器件和使用（000-1）面的碳化硅衬底的器件的制造方法。 通过优化栅极氧化后使用的热处理方法来制造具有高阻断电压和高沟道迁移率的SiC半导体器件。 制造半导体器件的方法包括以下步骤：在由具有（000-1）面取向的碳化硅形成的半导体区上形成栅极绝缘层，在栅极绝缘层上形成栅电极，在半导体上形成电极 区域，清洁半导体区域表面。 在800℃至1150℃的温度下，在含有1％或更多的H 2 O（水）蒸气的气氛中形成栅极绝缘层，以降低界面陷阱密度 栅极绝缘层和半导体区域之间的界面。

公开(公告)号：US20060057796A1

公开(公告)日：2006-03-16

申请号：US10531582

申请日：2003-10-03

申请人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi

发明人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi

IPC分类号： H01L21/8238

CPC分类号： H01L29/66477 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802

摘要： A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

摘要翻译： 具有低导通电阻和高阻断电压的碳化硅垂直MOSFET。 在第一导电类型的高浓度碳化硅衬底的表面上形成第一导电类型的低浓度碳化硅的第一沉积膜。 形成在第一沉积膜上的是第二沉积膜，其包括第二导电类型的高浓度栅极区域，其中第一区域被选择性地去除。 在第二沉积膜上形成第三沉积膜，其包括比选择性去除的第一区域宽的第二区域，第一导电类型的高浓度源区域和第二导电类型的低浓度栅极区域。 第一导电类型的低浓度基区形成为与第一和第二区域中的第一沉积膜接触。