公开(公告)号：US12298641B2

公开(公告)日：2025-05-13

申请号：US18638710

申请日：2024-04-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangcai Yuan ,  Hehe Hu ,  Ce Ning ,  Hui Guo ,  Fengjuan Liu ,  Dongfang Wang ,  Zhengliang Li ,  Jiayu He

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

Abstract: An array substrate and a manufacturing method therefor, and a display apparatus are provided. The array substrate includes an underlay substrate, and at least one first transistor, at least one data line and at least one pixel electrode disposed on the underlay substrate. The at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the underlay substrate, and orthographic projections of the first gate and the first active layer on the underlay substrate are at least partially overlapped. The first active layer is electrically connected to the data line and the pixel electrode, respectively. The data line is located on a side of the first active layer close to the underlay substrate, and the pixel electrode is located on a side of the first gate away from the underlay substrate.

公开(公告)号：US12276890B2

公开(公告)日：2025-04-15

申请号：US18005421

申请日：2022-03-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Binbin Tong ,  Lizhong Wang ,  Jianbo Xian ,  Liping Lei ,  Chunping Long ,  Yunping Di ,  Ce Ning

IPC: G02F1/1362 ,  G02F1/01 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1343

Abstract: At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.

公开(公告)号：US12233410B2

公开(公告)日：2025-02-25

申请号：US17292277

申请日：2020-01-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaochen Ma ,  Ce Ning ,  Chao Li ,  Jiayu He ,  Xueyuan Zhou ,  Xiao Zhang ,  Xin Gu ,  Zhengliang Li ,  Guangcai Yuan

IPC: B01L3/00

Abstract: A microfluidic channel backplane includes a base, and a plurality of microfluidic channels, a sample-adding channel and an enrichment channel that are disposed above the base. Each microfluidic channel of the plurality of microfluidic channels includes a first end and a second end. The sample-adding channel is communicated with first ends of the plurality of microfluidic channels. The enrichment channel includes a first enrichment sub-channel and a second enrichment sub-channel. The first enrichment sub-channel is communicated with second ends of the plurality of microfluidic channels, and one end of the second enrichment sub-channel is communicated with the first enrichment sub-channel.

公开(公告)号：US12213372B2

公开(公告)日：2025-01-28

申请号：US17732781

申请日：2022-04-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei Yang ,  Guangcai Yuan ,  Ce Ning ,  Xinhong Lu ,  Tianmin Zhou ,  Xin Yang

IPC: H01L51/00 ,  H10K59/124 ,  H10K59/131 ,  H10K77/10

Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area for bonding a circuit board, wherein the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, wherein the display panel further includes: a first groove located in the bending area and having a depth substantially identical to that of the first via holes; and a metal trace, connecting a trace in the display area to the circuit board.

公开(公告)号：US12183824B2

公开(公告)日：2024-12-31

申请号：US17611156

申请日：2021-01-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jie Huang ,  Jiayu He ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Fengjuan Liu ,  Nianqi Yao ,  Kun Zhao ,  Tianmin Zhou ,  Jiushi Wang ,  Zhongpeng Tian

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  G02F1/1368

Abstract: The present disclosure relates to the field of display technologies, and in particular to a thin film transistor and a method for manufacturing the same, an array substrate and a display device. An active layer of the thin film transistor includes at least two metal oxide semi-conductor layers, the at least two metal oxide semi-conductor layers include a channel layer and a first protection layer, and metals in the channel layer include tin, and at least one of indium, gallium and zinc. The first protection layer includes praseodymium used to absorb photo-generated electrons from at least one of the channel layer and the first protection layer which is under light irradiation and reduce a photo-generated current caused by the light irradiation.

公开(公告)号：US20240194161A1

公开(公告)日：2024-06-13

申请号：US17908359

申请日：2021-08-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Guangcai Yuan ,  Ce Ning ,  Hehe Hu ,  Nianqi Yao ,  Xin Xie ,  Yifang Huang ,  Liping Lei ,  Chen Xu

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0286

Abstract: A display substrate and a display panel are provided, the display substrate includes a first gate driver circuit and a second gate driver circuit that are respectively arranged on a first side and a second side of a display region; the first gate driver circuit includes a plurality of first shift register units arranged in a first direction, each first shift register unit includes a first thin film transistor; the second gate driver circuit includes a plurality of second shift register units arranged in the first direction, each second shift register unit includes a second thin film transistor having the same function as the first thin film transistor; an average turn-on current of at least one first thin film transistor is Ion1, and an average turn-on current of at least one second thin film transistor is Ion2, Ion1>Ion2.

公开(公告)号：US20240162247A1

公开(公告)日：2024-05-16

申请号：US17772761

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Fuqiang Li ,  Zhen Zhang ,  Zhenyu Zhang ,  Lizhong Wang ,  Ce Ning ,  Yunping Di ,  Zheng Fang ,  Jiahui Han ,  Chenyang Zhang ,  Yawei Wang ,  Chengfu Xu

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  H01L27/1288 ,  H01L27/1222

Abstract: Disclosed are a thin film transistor and a manufacturing method therefor, a displaying base plate and a displaying apparatus. The thin film transistor includes an active layer, a first insulating layer and a gate layer which are disposed in stack, wherein the active layer includes a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area includes a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction; the gate layer includes a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area; and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area.

公开(公告)号：US20240103328A1

公开(公告)日：2024-03-28

申请号：US17765769

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/136286 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

公开(公告)号：US11905163B2

公开(公告)日：2024-02-20

申请号：US16753362

申请日：2019-04-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaochen Ma ,  Guangcai Yuan ,  Ce Ning ,  Xin Gu ,  Xiao Zhang ,  Chao Li

IPC: B81B1/00 ,  B81C1/00 ,  B01L3/00

CPC classification number: B81B1/002 ,  B01L3/502715 ,  B81C1/00071 ,  B01L2300/0645 ,  B81B2201/05 ,  B81B2203/0338 ,  B81C2201/0111 ,  B81C2201/036

Abstract: A micro-nano channel structure, a method for manufacturing the micro-nano channel structure, a sensor, a method for manufacturing the sensor, and a microfluidic device are provided by the embodiments of the present disclosure. The micro-nano channel structure includes: a base substrate; a base layer, on the base substrate and including a plurality of protrusions; and a channel wall layer, on a side of the plurality of the protrusions away from the base substrate, and the channel wall layer has a micro-nano channel; a recessed portion is provided between adjacent protrusions of the plurality of the protrusions, and an orthographic projection of the micro-nano channel on the base substrate is located within an orthographic projection of the recessed portion on the base substrate.

公开(公告)号：US10483129B2

公开(公告)日：2019-11-19

申请号：US15717527

申请日：2017-09-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jing Feng ,  Seung Jin Choi ,  Fangzhen Zhang ,  Wusheng Li ,  Zhijun Lv ,  Ce Ning ,  Jiushi Wang

IPC: H01L21/4763 ,  H01L21/027 ,  H01L29/66 ,  H01L29/786 ,  G03F7/00 ,  H01L27/12 ,  G03F7/38 ,  G03F7/20 ,  G03F7/40 ,  H01L21/321

Abstract: The disclosure discloses a method for roughening a surface of a metal layer, a thin film transistor, and a method for fabricating the same. The method for roughening the surface of a metal layer includes: forming a first photo-resist layer on the surface of the metal layer, and processing the first photo-resist layer at high temperature; and stripping the first photo-resist layer to roughen the surface of the metal layer.