公开(公告)号：US07266169B2

公开(公告)日：2007-09-04

申请号：US10243495

申请日：2002-09-13

申请人： Bo Zhang

发明人： Bo Zhang

IPC分类号： H03D3/24

CPC分类号： H03K5/13 ,  H03K2005/00065 ,  H03L7/0814

摘要： A phase interpolator includes a plurality of clock phase input sections, a plurality of clock phase switching sections, a plurality of current sources and a load. Each of the clock phase input sections is coupled to receive one of a plurality of reference clock phases (e.g., 0°, 90°, 180°, and 270°). The plurality of current sources is selectively coupled to the plurality of clock phase input sections via the clock phase switching sections based on a phase control signal. The number of current sources corresponds to the phase granularity between the reference clock phases. The load is coupled to a phase adjusted clock signal in accordance with the phase control signal.

摘要翻译： 相位插值器包括多个时钟相位输入部分，多个时钟相位切换部分，多个电流源和负载。 每个时钟相位输入部分被耦合以接收多个参考时钟相位（例如，0°，90°，180°和270°）中的一个。 基于相位控制信号，多个电流源经由时钟相位切换部选择性地耦合到多个时钟相位输入部。 电流源的数量对应于参考时钟相位之间的相位粒度。 负载根据相位控制信号耦合到相位调整的时钟信号。

公开(公告)号：US20070075350A1

公开(公告)日：2007-04-05

申请号：US11411648

申请日：2006-04-26

申请人： Hooman Darabi ,  Oiang Li ,  Bo Zhang

发明人： Hooman Darabi ,  Oiang Li ,  Bo Zhang

IPC分类号： H01L29/94

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L28/87 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

摘要翻译： 至少第一电容器形成在衬底上并连接到差分电路的第一差分节点，并且第一电容器可以是可变电容的。 第二电容器形成在衬底上并连接到差分电路的第二差分节点，并且第二电容器也可以是可变的。 第三电容器连接在第一差分节点和第二差分节点之间，并且至少部分地形成在第一电容器的上方。 以这种方式，可以在衬底上减小第一电容器和/或第二电容器的尺寸，并且可以响应于一个或多个电路的可变特性来调整第一和/或第二电容器的电容 差分电路的组件。

公开(公告)号：US20070014226A1

公开(公告)日：2007-01-18

申请号：US11172502

申请日：2005-06-29

申请人： Weimin Sun ,  Karl Wyatt ,  Bo Zhang

发明人： Weimin Sun ,  Karl Wyatt ,  Bo Zhang

IPC分类号： H04J3/10 ,  H04J1/12 ,  H04J15/00

CPC分类号： H04L25/49 ,  H04L25/03834 ,  H04L25/085

摘要： A method and apparatus is described herein for pulse shift modulation of output waveforms for reducing crosstalk on interconnects. Based on input pulses/bits, an output waveform is selectively delayed by a shift value to ensure transitions in a first direction occur in a first half of a period and transitions in a second direction occur in a second half of the period. When the same pulse shift modulation is implemented on surrounding traces, certain worst-case crosstalk scenarios are reduced; thus reducing crosstalk and increasing performance in power consumption and speed of data transfer.

摘要翻译： 这里描述了用于减少互连上的串扰的输出波形的脉冲移位调制的方法和装置。 基于输入脉冲/位，输出波形被选择性地延迟移位值，以确保在第一个方向的前半部分发生第一方向的转变，并且在该周期的后半段中发生第二方向的转变。 当在周围迹线上实现相同的脉冲移位调制时，某些最坏情况的串扰情景会减少; 从而减少串扰并提高功耗和数据传输速度。

公开(公告)号：US20060222014A1

公开(公告)日：2006-10-05

申请号：US11096603

申请日：2005-04-01

申请人： Bo Zhang

发明人： Bo Zhang

IPC分类号： H04J3/00

CPC分类号： H04N21/6437 ,  H04N21/23614 ,  H04N21/4348

摘要： Described herein is a method and system for formatting encoded video data. The encoder core makes use of unit structures with types that are undefined. These units are inserted into the encoder core output to carry additional information to a transport module. The transport module interprets the units for packetizing and/or multiplexing purposes. After being interpreted, the units may be taken out from the encoder core output, but there should be no adverse effects even if they are left in since no decoding process is defined for their particular type.

摘要翻译： 这里描述了用于格式化编码视频数据的方法和系统。 编码器核心使用具有未定义类型的单元结构。 这些单元插入到编码器核心输出端，以便将附加信息传送到传输模块。 传输模块将单元解释为打包和/或复用的目的。 在解读之后，可以从编码器核心输出中取出单元，但即使不存在不利影响，因为没有为其特定类型定义解码过程。

公开(公告)号：US20060134475A1

公开(公告)日：2006-06-22

申请号：US11016279

申请日：2004-12-17

申请人： Liqing Hu ,  Jianwei Xia ,  Bo Zhang

发明人： Liqing Hu ,  Jianwei Xia ,  Bo Zhang

IPC分类号： H01M8/18

CPC分类号： H01M8/04126

摘要： An air humidifying system includes an air humidifying device including a humidifying unit, having a dry air inlet and a humidified air outlet, for humidifying a flow of dry air from the dry air inlet to a humidified air exiting at the humidified air outlet. An air filtering unit has an air filtering inlet for guiding an ambient air as the dry air and an air filtering outlet communicating with the dry air inlet of the humidifying unit for purifying the dry air before entering into the humidifying unit. An air supplying unit has an air inlet port communicating with the humidified air outlet of the humidifying unit and an air outlet port adapted for communicating with an air inlet of the fuel cell stack, wherein the air supplying unit is adapted for guiding the humidified air into the fuel cell stack in a pressurized manner.

摘要翻译： 空气加湿系统包括：空气加湿装置，包括具有干燥空气入口和加湿空气出口的加湿单元，用于将来自干燥空气入口的干燥空气流加湿到在加湿空气出口处排出的加湿空气。 空气过滤单元具有用于引导作为干燥空气的环境空气的空气过滤入口和与加湿单元的干燥空气入口连通的空气过滤出口，用于在进入加湿单元之前净化干燥空气。 空气供给单元具有与加湿单元的加湿空气出口连通的空气入口和适于与燃料电池堆的空气入口连通的空气出口，其中空气供应单元适于将加湿空气引导到 燃料电池堆以加压的方式。

公开(公告)号：US20060014627A1

公开(公告)日：2006-01-19

申请号：US11230950

申请日：2005-09-19

申请人： Jian Zhang ,  Hwey Liow ,  Bo Zhang

发明人： Jian Zhang ,  Hwey Liow ,  Bo Zhang

IPC分类号： C04B35/488

CPC分类号： C04B35/488 ,  B01L3/0275 ,  B25B9/02 ,  B26B13/00 ,  C04B35/117 ,  C04B35/119 ,  C04B35/486 ,  C04B35/4885 ,  C04B35/63 ,  C04B35/632 ,  C04B35/634 ,  C04B35/63416 ,  C04B2235/3225 ,  C04B2235/3232 ,  C04B2235/3241 ,  C04B2235/3246 ,  C04B2235/3272 ,  C04B2235/449 ,  C04B2235/6022 ,  C04B2235/652 ,  C04B2235/6581 ,  C04B2235/6582 ,  C04B2235/80 ,  C04B2235/96

摘要： The invention provides partially stabilised zirconia and alumina based electro-static dissipative or ESD ceramic compositions. The proposed ceramic compositions include specific amounts of dopants comprising one or more metal oxides selected from iron oxide, chromium oxide and titanium oxide. The proposed ESD ceramic materials are made into useful industrial products by injection moulding and sintering technology. A novel binder system may optionally be used to make injection mouldable feedstock. Useful products produced by the invention include, for example, ESD ceramic tweezers tips, ESD ceramic dispensing needles, ESD ceramic scissors and blades and ESD ceramic wire bonding capillaries which retain their ESD properties at relatively low temperatures, for example, service temperatures from 25 to 500° C.

摘要翻译： 本发明提供部分稳定的氧化锆和氧化铝基静电消散或ESD陶瓷组合物。 所提出的陶瓷组合物包括特定量的包含一种或多种选自氧化铁，氧化铬和氧化钛的金属氧化物的掺杂剂。 所提出的ESD陶瓷材料通过注塑和烧结技术制成有用的工业产品。 可以任选地使用新的粘合剂体系来制备注射成型的原料。 本发明生产的有用的产品包括例如ESD陶瓷镊子尖端，ESD陶瓷分配针，ESD陶瓷剪刀和刀片以及在相对低的温度下保持其ESD特性的ESD陶瓷丝焊接毛细管，例如从25到 500°C

公开(公告)号：US20050190004A1

公开(公告)日：2005-09-01

申请号：US11120738

申请日：2005-05-03

申请人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

发明人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC分类号： H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H03B1/00

CPC分类号： H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

摘要翻译： 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US20050015638A1

公开(公告)日：2005-01-20

申请号：US10919093

申请日：2004-08-16

申请人： Bo Zhang

发明人： Bo Zhang

IPC分类号： H03K3/356 ,  H03K3/3562 ,  H03K5/00 ,  H03K17/041 ,  H03K17/693 ,  H03M9/00 ,  H04J3/04 ,  G06F1/12

CPC分类号： H03M9/00 ,  H03K3/356043 ,  H03K3/356139 ,  H03K3/3562 ,  H03K17/04106 ,  H03K17/693 ,  H03K2005/00208 ,  H04J3/047

摘要： In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

摘要翻译： 根据本发明，数据处理电路包括用于处理第一数据的第一数据路径。 第一数据路径包括第一数据存储电路。 提供第二数据路径用于处理第二数据。 第二数据路径包括第二数据存储电路。 具有耦合到第一数据路径的第一输入和耦合到第二数据路径的第二输入的多路复用器接收存储的值。 复用器包括耦合到时钟信号的选择输入。 延迟电路被配置为延迟第二数据存储电路中的第二数据的存储，其中第一数据存储电路响应于接收到第一定时信号而存储第一数据，并且第二数据存储电路存储第二数据作为响应 以接收第二定时信号。

公开(公告)号：US06781420B2

公开(公告)日：2004-08-24

申请号：US10243281

申请日：2002-09-12

申请人： Bo Zhang

发明人： Bo Zhang

IPC分类号： H03K1920

CPC分类号： H03K19/215 ,  H03K19/09432

摘要： Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the circuit configuration used to process a first logic input in the first logic unit is the same as the circuit configuration used to process a second logic input in the second logic unit, and the circuit configuration used to process the second logic input in the first logic unit is the same as the circuit configuration used to process the first logic input in the second logic unit. The present invention may be used for logic circuits that perform a variety of logical operations, such as XOR, AND, NAND, OR, or NOR.

摘要翻译： 本发明的实施例利用包括两个逻辑单元的对称逻辑电路来执行逻辑运算。 在对称逻辑电路中，用于处理第一逻辑单元中的第一逻辑输入的电路配置与用于处理第二逻辑单元中的第二逻辑输入的电路配置相同，并且用于处理第二逻辑单元的电路配置 第一逻辑单元中的逻辑输入与用于处理第二逻辑单元中的第一逻辑输入的电路配置相同。 本发明可以用于执行诸如XOR，AND，NAND，OR或NOR的各种逻辑操作的逻辑电路。

公开(公告)号：US06526109B1

公开(公告)日：2003-02-25

申请号：US09615627

申请日：2000-12-05

申请人： Charles Chang ,  Bo Zhang ,  Zhihao Lao

发明人： Charles Chang ,  Bo Zhang ,  Zhihao Lao

IPC分类号： H04L2500

CPC分类号： H03L7/089 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/087 ,  H04L7/033 ,  H04L7/0331

摘要： Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data. The delay control loops are low bandwidth, because the phase offset generally changes slowly, and because the loops should not respond to temporary upsets such as noise spikes. The delay control loops integrate the output of the bang-bang phase detector and use the output to control a decimated up down counter, which is then further used to control one or more variable delays. The counter can be pre-loaded with a default start point, and the bandwidth of the loops can be dynamically adjusted by changing the decimation ratio and sample periods of the loop.

摘要翻译： 现代光纤网络通常使用其中时钟与数据一起发送的编码来传送数据，例如以NRZ格式传送数据。 为了使用时钟来处理数据，必须从数据信号中提取时钟信号。 由于数据和时钟可能通过不同的电路路径，它们可能具有不同的传播延迟，并且可能导致时钟和数据之间的相位偏移。 随着数据传输速度的提高，数据和时钟相位偏移更有问题。 此外，数据/相位偏移通常不是常数，并且可以随各种变量而变化。 为了补偿变化的偏移，在相位检测器电路中插入一个或多个可变延迟。 可变延迟的定时由诸如亚历山大相位检测器之类的爆炸相位检测器控制，该相位检测器确定时钟是否领先，滞后或与数据同相。 延迟控制环路是低带宽，因为相位偏移通常会缓慢变化，并且因为环路不应该响应诸如噪声尖峰之类的临时故障。 延迟控制回路集成了爆炸相位检测器的输出，并使用输出来控制抽取的向上计数器，然后进一步用于控制一个或多个可变延迟。 计数器可以预加载一个默认的开始点，循环的带宽可以通过改变抽取比例和循环采样周期来动态调整。