公开(公告)号：US20050085163A1

公开(公告)日：2005-04-21

申请号：US10685588

申请日：2003-10-16

申请人： Chia-Lin Hsu ,  Shu-Hsien Lee ,  Chien-Chien Tsai ,  Hsiao-Ling Lu

发明人： Chia-Lin Hsu ,  Shu-Hsien Lee ,  Chien-Chien Tsai ,  Hsiao-Ling Lu

IPC分类号： B24B49/00 ,  B24B51/00 ,  H01L21/02

CPC分类号： H01L21/0209 ,  H01L21/02087

摘要： A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.

摘要翻译： 本发明公开了一种改善边缘剥离缺陷的方法。 根据本发明，通过在晶片上形成金属互连层之后，通过引入在晶片边缘处去除弱粘合膜和金属结构的步骤，可以保持晶片免受现有技术的边缘剥离缺陷的影响。 因此，本发明可以提高半导体制造的产量，并且减少半导体制造室的污染机会。

公开(公告)号：US06660627B2

公开(公告)日：2003-12-09

申请号：US10063133

申请日：2002-03-25

申请人： Shao-Chung Hu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu ,  Chia-Lin Hsu

发明人： Shao-Chung Hu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu ,  Chia-Lin Hsu

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/31051

摘要： A method for planarization of a semiconductor wafer with a high selectivity is describe. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method includes performing a chemical mechanical polishing (CMP) process on the barrier layer so as to expose the stop layer, and removing the stop layer. The polishing selectivity of the barrier layer relative to the stop layer is greater than 50. Since the material of stop layer is different from the material of barrier layer, the high selectivity is easily achieved. Thus, the surface of semiconductor wafer can be highly planarized.

摘要翻译： 描述了一种以高选择性平坦化半导体晶片的方法。 半导体晶片具有硬掩模，设置在硬掩模上的阻挡层和设置在阻挡层上的阻挡层。 该方法包括在阻挡层上进行化学机械抛光（CMP）处理，以露出停止层，并除去停止层。 阻挡层相对于停止层的抛光选择性大于50.由于阻挡层的材料与阻挡层的材料不同，因此容易实现高选择性。 因此，半导体晶片的表面可以被高度平坦化。

公开(公告)号：US09318567B2

公开(公告)日：2016-04-19

申请号：US13603425

申请日：2012-09-05

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC分类号： H01L21/31 ,  H01L21/84 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.

摘要翻译： 制造半导体器件的方法包括以下步骤。 首先，提供至少包括翅片结构和至少设置在其上的栅极半导体层的半导体衬底。 栅极半导体层覆盖翅片结构的一部分。 然后沉积牺牲层以完全覆盖翅片结构。 随后，翅片结构的顶表面通过蚀刻工艺从牺牲层露出。 然后沉积材料层，其共形地覆盖栅极半导体层，鳍结构和牺牲层。 最后，蚀刻材料层直到翅片结构的顶表面露出，并且在栅极半导体层的侧表面上同时形成第一间隔物。

公开(公告)号：US08796695B2

公开(公告)日：2014-08-05

申请号：US13530127

申请日：2012-06-22

申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC分类号： H01L29/772

CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

摘要翻译： 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

公开(公告)号：US20130288448A1

公开(公告)日：2013-10-31

申请号：US13459262

申请日：2012-04-30

申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee ,  Min-Chung Cheng

发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee ,  Min-Chung Cheng

IPC分类号： H01L21/762

CPC分类号： H01L21/0237 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/66795

摘要： A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening.

摘要翻译： 半导体工艺包括以下步骤。 提供半导体衬底。 半导体衬底具有图案化隔离层，并且图案化隔离层具有暴露半导体衬底的硅区域的开口。 在开口的侧壁上形成富硅层。 执行外延工艺以在开口中的硅区域上形成外延结构。

公开(公告)号：US20130270612A1

公开(公告)日：2013-10-17

申请号：US13447286

申请日：2012-04-16

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

摘要： The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

摘要翻译： 本发明提供一种非平面FET，其包括衬底，鳍结构，栅极和栅极电介质层。 翅片结构设置在基板上。 翅片结构包括与基底相邻的第一部分，其中第一部分朝向基底的一侧收缩。 门设置在翅片结构上。 栅介质层设置在鳍结构和栅极之间。 本发明还提供一种制造非平面FET的方法。

公开(公告)号：US07718536B2

公开(公告)日：2010-05-18

申请号：US11160262

申请日：2005-06-16

申请人： Chia-Lin Hsu

发明人： Chia-Lin Hsu

IPC分类号： H01L21/461

CPC分类号： H01L21/3212

摘要： A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

摘要翻译： 描述了一种预镶嵌结构的平面化方法，其中预镶嵌结构包括设置在其中具有镶嵌开口的第一材料层上的金属硬掩模和填充镶嵌开口并覆盖金属的第二材料层 硬面膜 使用第一浆料进行第一CMP步骤以除去镶嵌开口外部的第二材料层。 使用第二浆料进行第二CMP步骤以除去金属硬掩模。

公开(公告)号：US20080026582A1

公开(公告)日：2008-01-31

申请号：US11868538

申请日：2007-10-08

申请人： Chia-Lin Hsu

发明人： Chia-Lin Hsu

IPC分类号： H01L21/461

CPC分类号： H01L21/3212

摘要： A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

摘要翻译： 描述了一种预镶嵌结构的平面化方法，其中预镶嵌结构包括设置在其中具有镶嵌开口的第一材料层上的金属硬掩模和填充镶嵌开口并覆盖金属的第二材料层 硬面膜 使用第一浆料进行第一CMP步骤以除去镶嵌开口外部的第二材料层。 使用第二浆料进行第二CMP步骤以除去金属硬掩模。

公开(公告)号：US20070037389A1

公开(公告)日：2007-02-15

申请号：US11161650

申请日：2005-08-11

申请人： Shu-Jen Chen ,  Chia-Lin Hsu

发明人： Shu-Jen Chen ,  Chia-Lin Hsu

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/288

摘要： A process for electroless plating a metal cap barrier on a substrate is disclosed. Copper metallization is formed on the substrate such that the substrate has an exposed top surface of a copper line. The exposed top surface of the copper line is pre-cleaned. The pre-cleaned exposed top surface of the copper line is exposed to an activation solution. The exposed top surface of the copper line of the substrate is then in-situ annealed in an vapor ambient containing a flow of alcohol and carrier gas at a temperature less than 400° C. The metal cap barrier is selectively deposited onto the exposed top surface of the copper line by performing electroless plating.

摘要翻译： 公开了一种用于化学镀金属帽阻挡层的方法。 在基板上形成铜金属化，使得基板具有暴露的铜线顶表面。 铜线暴露的顶部表面被预先清洁。 预先清洁的铜线暴露的顶表面暴露于活化溶液。 然后在小于400℃的温度下，在含有醇和载气流的蒸汽环境中将衬底的铜线的暴露的顶表面进行原位退火。将金属帽屏障选择性地沉积到暴露的顶表面 的铜线。

公开(公告)号：US06709544B2

公开(公告)日：2004-03-23

申请号：US10064526

申请日：2002-07-24

申请人： Shao-Chung Hu ,  Chia-Lin Hsu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu

发明人： Shao-Chung Hu ,  Chia-Lin Hsu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu

IPC分类号： B24B700

CPC分类号： B24B37/20 ,  B24B37/042

摘要： The present invention related to a CMP equipment, compatible with the existing manufacture processes. The CMP equipment of the present invention employs strip polishing platens that can be smaller than the wafer size, so that the layout is compact and the space is effectively utilized, leading to high throughput and efficient production management. The present invention provides a CMP equipment that offers greater flexibility in performing CMP for different fabrication processes through the choices of various polishing pads and/or polishing slurry.

摘要翻译： 本发明涉及与现有制造工艺兼容的CMP设备。 本发明的CMP设备采用可以比晶片尺寸小的带状抛光压板，使得布局紧凑并且有效地利用空间，导致高产量和高效的生产管理。 本发明提供一种CMP设备，其通过选择各种抛光垫和/或抛光浆料，为不同的制造工艺执行CMP提供更大的灵活性。