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    ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY AND ARRAY
    41.
    发明申请
    ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY AND ARRAY 审中-公开
    电气可变非易失性存储器和阵列

    公开(公告)号：US20080203464A1

    公开(公告)日：2008-08-28

    申请号：US11932481

    申请日：2007-10-31

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/76 ,  H01L21/336

    CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: A memory device, array and method of arranging where the memory device includes a memory cell region including a plurality of memory cells. Each memory cell includes a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. Cell lines extend among the memory cells. A connection region is provided for electrically coupling contacts and one or more of the cell lines. A non-memory region has embedded logic. Memory cells are arrayed at a cell pitch, with cell lines extending from cell to cell and arrayed substantially at the cell pitch, and with contacts arrayed substantially at the cell pitch forming a high density memory device.

    Abstract translation: 一种存储器件，阵列和方法，其布置存储器件包括包括多个存储器单元的存储单元区域的位置。 每个存储单元包括源极，漏极和源极和漏极之间的沟道，沟道电介质，电荷存储区域和靠近电荷存储区域的电可改变的导体材料系统。 单元线在存储单元之间延伸。 提供连接区域用于电耦合触点和一个或多个细胞系。 非内存区域具有嵌入式逻辑。 存储器单元以单元间距排列，细胞系从单元延伸到单元并基本上以单元间距排列，并且基本上以单元间距排列的接触形成高密度存储器件。

    Low power electrically alterable nonvolatile memory cells and arrays
    42.
    发明授权
    Low power electrically alterable nonvolatile memory cells and arrays 有权
    低功率电气可变非易失性存储器单元和阵列

    公开(公告)号：US07411244B2

    公开(公告)日：2008-08-12

    申请号：US11234646

    申请日：2005-09-23

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/06 ,  H01L21/336

    CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/26586 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/47 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Apparatus on cell architecture are provided for the nonvolatile memory cells. Additionally, apparatus on array architectures are provided for constructing the nonvolatile memory cells in memory array. Method on manufacturing such memory cells and array architectures are provided.

    Abstract translation: 提供具有导体滤波器系统，导体 - 绝缘体系统和电荷注入系统的非易失性存储单元。 导体滤波器系统为电荷载流子提供带通滤波功能，电荷滤波功能和质量滤波功能。 导体 - 绝缘体系统提供图像强制屏障降低效应以收集电荷载体。 电荷注入系统包括导体 - 滤波器系统和导体 - 绝缘体系统，其中导体 - 滤波器系统的滤波器接触导体 - 绝缘体系统的导体。 为非易失性存储单元提供了单元结构的装置。 此外，提供了阵列架构上的装置用于构建存储器阵列中的非易失性存储单元。 提供了制造这种存储单元和阵列架构的方法。

    High voltage FET gate structure
    43.
    发明授权
    High voltage FET gate structure 有权
    高压FET栅极结构

    公开(公告)号：US07375398B2

    公开(公告)日：2008-05-20

    申请号：US11138888

    申请日：2005-05-26

    Applicant: Bin Wang ,  Chih-Hsin Wang

    Inventor： Bin Wang ,  Chih-Hsin Wang

    IPC: H01L23/62

    CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

    Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

    Abstract translation: 用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底，衬底内的第一阱和第二阱。 第一和第二阱限定p-n结。 第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。 第三阱至少部分地位于第一阱中，包括第二类型的掺杂植入物，并且适于接收源极接触。 这样，第三井在第一井内定义了自身与第二井之间的通道。 通道上设置一个门。 栅极的至少第一部分设置在p-n结上方，并且包括第一类型的掺杂植入物。 许多排列允许掺杂栅极的其余部分。

    RF tags affixed in manufactured elements
    45.
    发明申请
    RF tags affixed in manufactured elements 有权

    公开(公告)号：US20060290504A1

    公开(公告)日：2006-12-28

    申请号：US11356584

    申请日：2006-02-17

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: G08B13/14

    CPC classification number: G08B13/2445

    Abstract: A system for tracking elements employing fixed tags that are permanently attached to elements. The tags include radio-frequency (RF) communication units that are adapted for wireless communication with RF communicators. The RF tags are permanently affixed to elements as part of the manufacturing of products such as cell phones, PDA's, computers, routers and other electronic equipment. The RF tags are installed during manufacturing in a manner that resists tampering and interference. The RF tags are installed with mechanical barriers to access and are hidden from view in non-user accessible locations.

    Inverter non-volatile memory cell and array system
    47.
    发明申请
    Inverter non-volatile memory cell and array system 有权
    逆变器非易失性存储单元和阵列系统

    公开(公告)号：US20060209598A1

    公开(公告)日：2006-09-21

    申请号：US11084214

    申请日：2005-03-17

    Applicant: Bin Wang ,  Chih-Hsin Wang ,  William Colleran

    Inventor： Bin Wang ,  Chih-Hsin Wang ,  William Colleran

    IPC: G11C16/04

    CPC classification number: G11C16/10

    Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

    Abstract translation: NVM阵列包括包括浮动栅极，双晶体管，逆变器存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

    Method of forming floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells made thereby
    48.
    发明授权
    Method of forming floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells made thereby 失效
    用弹道电荷注入器形成具有沟槽结构的浮栅存储单元的方法，以及由此形成的存储单元阵列

    公开(公告)号：US07015102B2

    公开(公告)日：2006-03-21

    申请号：US11006237

    申请日：2005-04-13

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H10L21/336

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

    Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes an electrical conductive floating gate formed in a trench in a semiconductor substrate, and an electrical conductive control gate having a portion disposed over and insulated from the floating gate. An electrical conductive tunneling gate is disposed over and insulated from the control gate by an insulating layer to form a tri-layer structure permitting both electron and hole charges tunneling through at similar tunneling rate. Spaced apart source and drain regions are formed with the source region disposed adjacent to and insulated from a lower portion of the floating gate, and with the drain region disposed adjacent to and insulated from an upper portion of the floating gate with a channel region formed therebetween and along a sidewall of the trench.

    Abstract translation: 一种形成浮栅存储器单元阵列的方法，以及由此形成的阵列，其中每个存储单元包括形成在半导体衬底中的沟槽中的导电浮动栅极，以及导电控制栅极，其具有设置在绝缘上的部分 从浮动门。 导电隧道栅极通过绝缘层设置在控制栅极之上并与控制栅极绝缘，以形成三层结构，允许电子和空穴电荷以类似的隧穿速率隧穿。 间隔开的源极和漏极区域形成有源极区域，其设置为与浮置栅极的下部相邻并与其绝缘，并且漏极区域设置成与浮置栅极的上部相邻并与之隔绝，其中沟道区域形成在其间 并且沿着沟槽的侧壁。

    Electrically alterable non-volatile memory cell
    49.
    发明申请
    Electrically alterable non-volatile memory cell 失效

    公开(公告)号：US20060035424A1

    公开(公告)日：2006-02-16

    申请号：US10919555

    申请日：2004-08-16

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L21/8234

    CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L29/42332 ,  H01L29/7885 ,  H01L29/792

    Abstract: A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region. The source and the drain are formed in the well and having the p-type conductivity with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel region by an insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the insulator onto the charge storage region. The memory cell can be implemented in a conventional logic CMOS process.

    Electrically alterable memory cell
    50.
    发明申请
    Electrically alterable memory cell 有权
    电可变存储单元

    公开(公告)号：US20060006454A1

    公开(公告)日：2006-01-12

    申请号：US11120691

    申请日：2005-05-02

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/76

    CPC classification number: H01L29/42324 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: A nonvolatile memory cell is provided. The cell has a charge filter, a tunneling gate, a ballistic gate, a charge storage layer, a source, and a drain with a channel defined between the source and drain. The charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage layer while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. Further embodiments of the present invention provide a cell having a charge filter, a supplier gate, a tunneling gate, a ballistic gate, a source, a drain, a channel, and a charge storage layer. The present invention further provides an energy band engineering method permitting the memory cell be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

    Abstract translation: 提供非易失性存储单元。 电池具有在源极和漏极之间限定的沟道的电荷滤波器，隧道栅极，弹道栅极，电荷存储层，源极和漏极。 电荷滤波器允许将一种极性类型的载流子从隧道栅极通过阻挡材料和弹道栅传输到电荷存储层，同时阻止相反极性的电荷载体从弹道栅极传输到隧道栅极。 本发明的另外的实施例提供了一种具有电荷滤波器，供电门，隧道门，弹道门，源极，漏极，沟道和电荷存储层的电池。 本发明进一步提供了允许存储器单元在不受到电介质击穿，不受冲击电离和不期望的RC影响的干扰的情况下运行的能带工程方法。

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