公开(公告)号：US20110128809A1

公开(公告)日：2011-06-02

申请号：US12769456

申请日：2010-04-28

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh-Ming Chih

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh-Ming Chih

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12

摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.

摘要翻译： 存储器集成电路具有访问存储器集成电路的存储单元的控制电路。 控制电路响应于包括第一命令和第二命令的命令。 第一个命令指定高位地址位集合。 第二个命令指定低位地址位集合。 地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。 第一个命令和第二个命令在命令代码中有所不同。

公开(公告)号：US20110128791A1

公开(公告)日：2011-06-02

申请号：US12834686

申请日：2010-07-12

申请人： Yi-Fan Chang ,  Cheng Ming Yih ,  Su-chueh Lo ,  Jian Shing Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yi-Fan Chang ,  Cheng Ming Yih ,  Su-chueh Lo ,  Jian Shing Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/06 ,  G11C16/16

CPC分类号： G11C16/14 ,  G11C16/344 ,  G11C16/3477

摘要： Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.

摘要翻译： 各种讨论的方法包括在擦除验证和擦除擦除操作的子操作期间改进擦除组的边缘字线和中心字线的分组。 在另一种方法中，改变边缘字线的电压电平以解决擦除组的过擦除问题，并且还提高擦除时间性能。 另一种方法使用虚拟字线。

公开(公告)号：US20110085380A1

公开(公告)日：2011-04-14

申请号：US12970222

申请日：2010-12-16

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.

摘要翻译： 一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。 每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。 耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。 在编程方法的实施例中，对应的数据分别输入到数据缓冲器。 对应于第n阶段的数据被编程到目标多级单元中。 修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理 根据第n个编程验证电压。 重复上述步骤直到n等于最大值，n为正整数。

公开(公告)号：US20110016291A1

公开(公告)日：2011-01-20

申请号：US12813395

申请日：2010-06-10

申请人： Yulan Kuo ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yulan Kuo ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G06F12/06

CPC分类号： G06F9/30076 ,  G06F9/30189 ,  G06F9/342

摘要： An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address.

摘要翻译： 集成电路存储器件具有存储器阵列和具有至少第一寻址模式的控制逻辑，其中指令包括第一指令代码和第一长度的地址; 以及第二寻址模式，其中指令包括第一指令代码和第二长度的地址。 地址的第一个长度与地址的第二个长度不同。

公开(公告)号：US20100054045A1

公开(公告)日：2010-03-04

申请号：US12204009

申请日：2008-09-04

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C7/00

CPC分类号： G11C16/24 ,  G11C16/26

摘要： A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.

摘要翻译： 存储器包括多个存储区域，每个存储器区域包括目标存储器单元，源极线，位线和读取控制电路。 源极线耦合到目标存储器单元的第一端子。 位线耦合到目标存储器单元的第二端子。 读取控制电路用于选择性地向源极线施加工作电压。

公开(公告)号：US20090201060A1

公开(公告)日：2009-08-13

申请号：US12027285

申请日：2008-02-07

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  H03K5/06 ,  H03K2005/00195

摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

摘要翻译： 提供了应用在SMD块中的时钟同步电路。 时钟同步电路包括多个时钟同步单元级。 时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生 用于触发前级延迟单元各级的输出时钟的短脉冲。

公开(公告)号：US20090116293A1

公开(公告)日：2009-05-07

申请号：US11976975

申请日：2007-10-30

申请人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chun-Yi Lee ,  Yung-Feng Lin ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C5/02

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C16/08

摘要： A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

摘要翻译： 公开了一种用于对其字线进行充电的存储器和方法。 存储器包括第一字线驱动器，第一字线和第一开关。 第一字线驱动器连接到用于接收第一控制信号的第一操作电压。 第一字线包括连接到第一字线驱动器的输出端的起始端。 第一开关连接到第一字线的第二工作电压和端子。 第二工作电压不小于第一工作电压。 当第一字线驱动器由第一控制信号控制以开始向第一字线充电时，第一开关同时导通，以为第一字线提供另一充电路径，直到第一字线被充电到第一操作 电压。

公开(公告)号：US20080304337A1

公开(公告)日：2008-12-11

申请号：US12174115

申请日：2008-07-16

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G11C7/00

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C11/5671

摘要： A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively, wherein each of the 2n level corresponds to a storage status of n bits, and most significant bits of the storage statuses which level 0 to level 2n/2−1 correspond to are different from most significant bits of the storage statuses which level 2n/2 to level 2n−1 correspond to. Next, a target data is divided into n portions and the divided target data is written into n temporary memories respectively. Then, n bits of the target data are written into the multi-level cell. Each of the n bits data is collected from each of the n temporary memories.

摘要翻译： 提供了访问存储器的方法。 存储器包括许多多级单元，每个单元具有至少一个能存储2n位的存储器，n是正整数。 访问存储器的方法包括以下步骤：首先，将存储器的阈值电压分别定义为2n级，其中2n级中的每一级对应于n位的存储状态，存储状态的最高有效位为0级 等级2n / 2-1对应于不同于2n / 2到2n-1级对应的存储状态的最高有效位。 接下来，目标数据被分成n个部分，分割的目标数据被分别写入n个临时存储器。 然后，将目标数据的n位写入多级单元。 从n个临时存储器中的每一个收集n位数据中的每一个。

公开(公告)号：US5955893A

公开(公告)日：1999-09-21

申请号：US767447

申请日：1996-12-16

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yin-Shang Liu

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yin-Shang Liu

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： An embodiment of the invention provides a buffer circuit having reduced power consumption. The buffer circuit comprises a power saving switch coupled to a buffer at a bias node. The buffer has an input that is adapted to receive input voltages at TTL levels, for example, and has an output adapted to provide output voltages at CMOS levels, for example. The power saving switch includes a level shifter and a voltage control circuit both coupled to the bias node. The output voltage of the buffer is fed back to the power saving switch. When the output voltage is at a low CMOS level, the power saving switch uses the voltage control circuit to provide a first bias voltage to the bias node. When the output voltage is at a high CMOS level, the power saving switch uses the level shifter to provide a second bias voltage to the bias node. The second bias voltage is chosen such that it prevents current flow between the bias node and the buffer at a predetermined input cutoff voltage. The level shifter provides a relatively constant second bias voltage by providing a relatively constant voltage shift V.sub.LS between a level shifter reference voltage V.sub.ref and the bias node. In the present embodiment, this voltage shift V.sub.LS is the absolute value of the gate to source threshold voltage of a FET. Accordingly, the second bias voltage is V.sub.ref -V.sub.LS. In one embodiment, the voltage control circuit includes a second level shifter to provide the first bias voltage.

摘要翻译： 本发明的实施例提供了具有降低的功耗的缓冲电路。 缓冲电路包括耦合到偏置节点处的缓冲器的省电开关。 例如，缓冲器具有适于以TTL电平接收输入电压的输入，并且具有适于在CMOS电平处提供输出电压的输出。 省电开关包括电平转换器和两个耦合到偏置节点的电压控制电路。 缓冲器的输出电压反馈给省电开关。 当输出电压处于低CMOS电平时，省电开关使用电压控制电路向偏置节点提供第一偏置电压。 当输出电压处于高CMOS电平时，省电开关使用电平移位器向偏置节点提供第二偏置电压。 第二偏置电压被选择为使得其在预定的输入截止电压下防止偏置节点和缓冲器之间的电流流动。 电平移位器通过在电平移位器参考电压Vref和偏置节点之间提供相对恒定的电压偏移VLS来提供相对恒定的第二偏置电压。 在本实施例中，该电压偏移VLS是FET的栅极 - 源极阈值电压的绝对值。 因此，第二偏置电压为Vref-VLS。 在一个实施例中，电压控制电路包括提供第一偏置电压的第二电平移位器。

公开(公告)号：US5875152A

公开(公告)日：1999-02-23

申请号：US751513

申请日：1996-11-15

申请人： Yin-Shang Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Ray-Lin Wan

发明人： Yin-Shang Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Ray-Lin Wan

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  H03K5/1534 ,  G11C8/00 ,  H03K5/22

CPC分类号： H03K5/1534 ,  G11C7/22 ,  G11C8/18

摘要： The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.

摘要翻译： 本发明提供一种新的（ATD）地址转换检测电路，用于具有任意数量的地址线的地址总线。 公开了一种包括第一和第二电路和间隔定时器的ATD电路。 第一电路具有第一和第二输入和输出。 第一电路在第一输入端接收对应于地址总线的一个或多个地址中的转变的改变信号。 作为响应，第一电路的输出从初始第一状态转变到第二状态。 第一电路还响应于第二输入端的复位命令将输出返回到第一状态。 间隔定时器具有耦合到第一电路的第二输入和输入的输出。 响应于输入的初始化命令的间隔定时器启动定时间隔，并且在定时间隔之后在输出端产生复位命令。 第二电路具有耦合到间隔定时器和输入的输入的输出。 响应于输入端的变化信号的第二电路在输出端产生初始化命令。 该电路在第一电路的输出处提供第二状态，包括在一系列变化信号中最后接收的信号。 这确保在允许存储器访问之前已经检测到所有地址转换。