公开(公告)号：US5875152A

公开(公告)日：1999-02-23

申请号：US751513

申请日：1996-11-15

申请人： Yin-Shang Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Ray-Lin Wan

发明人： Yin-Shang Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Ray-Lin Wan

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  H03K5/1534 ,  G11C8/00 ,  H03K5/22

CPC分类号： H03K5/1534 ,  G11C7/22 ,  G11C8/18

摘要： The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.

摘要翻译： 本发明提供一种新的（ATD）地址转换检测电路，用于具有任意数量的地址线的地址总线。 公开了一种包括第一和第二电路和间隔定时器的ATD电路。 第一电路具有第一和第二输入和输出。 第一电路在第一输入端接收对应于地址总线的一个或多个地址中的转变的改变信号。 作为响应，第一电路的输出从初始第一状态转变到第二状态。 第一电路还响应于第二输入端的复位命令将输出返回到第一状态。 间隔定时器具有耦合到第一电路的第二输入和输入的输出。 响应于输入的初始化命令的间隔定时器启动定时间隔，并且在定时间隔之后在输出端产生复位命令。 第二电路具有耦合到间隔定时器和输入的输入的输出。 响应于输入端的变化信号的第二电路在输出端产生初始化命令。 该电路在第一电路的输出处提供第二状态，包括在一系列变化信号中最后接收的信号。 这确保在允许存储器访问之前已经检测到所有地址转换。

公开(公告)号：US6031757A

公开(公告)日：2000-02-29

申请号：US825879

申请日：1997-04-02

申请人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Yin-Shang Liu ,  Yao-Wu Cheng

发明人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Yin-Shang Liu ,  Yao-Wu Cheng

IPC分类号： G11C16/22 ,  G11C16/04

CPC分类号： G11C16/22

摘要： A user-programmable write protection scheme provides flexibility and superior write protect features for an integrated circuit memory which comprises an array of non-volatile erasable and programmable memory cells, including a plurality of sectors. Command logic detects command sequences indicating operations for the array, including a program operation, a sector erase operation, a read operation, a sector lock operation, and a sector unlock operation. The sector protect logic includes sector lock memory, including non-volatile memory cells that store sector lock signals for at least one sector in the array. Among other functions, the sector protect logic: 1) inhibits sector erase and program operations to a particular sector in response to a set sector lock signal corresponding to the particular sector, and to a first state of control signals in the set of control signals; 2) enables sector erase and program operations in response to a reset sector lock signal corresponding to the particular sector, and to the first state of control signals in the set of control signals; 3) inhibits sector erase and program operations to the particular sector independent of the sector lock signal in response to a second state of control signals in the set of control signals; and 4) enables sector erase and program operations independent of the sector lock signal in response to a third state of control signals in the set of control signals.

摘要翻译： PCT No.PCT / US96 / 18674 Sec。 371日期1997年4月2日 102（e）日期1997年4月2日PCT提交1996年11月22日PCT公布。 第WO98 / 22950号公报 日期1998年5月28日用户可编程写保护方案为集成电路存储器提供灵活性和出色的写保护功能，其包括包括多个扇区的非易失性可擦除和可编程存储器单元的阵列。 命令逻辑检测指示阵列的操作的命令序列，包括程序操作，扇区擦除操作，读取操作，扇区锁定操作和扇区解锁操作。 扇区保护逻辑包括扇区锁定存储器，包括存储阵列中的至少一个扇区的扇区锁定信号的非易失性存储器单元。 在其他功能中，扇区保护逻辑：1）响应于对应于特定扇区的设置扇区锁定信号，以及控制信号组中的控制信号的第一状态，禁止对特定扇区的扇区擦除和编程操作; 2）响应于对应于特定扇区的复位扇区锁定信号和控制信号组中的控制信号的第一状态使能扇区擦除和编程操作; 3）响应于该组控制信号中的控制信号的第二状态，禁止与扇区锁定信号无关的扇区擦除和编程操作到特定扇区; 和4）响应于该组控制信号中的控制信号的第三状态，使扇区擦除和编程操作独立于扇区锁定信号。

公开(公告)号：US06219290B1

公开(公告)日：2001-04-17

申请号：US09172274

申请日：1998-10-14

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  I-Long Lee ,  Yin-Shang Liu ,  Ray-Lin Wan

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  I-Long Lee ,  Yin-Shang Liu ,  Ray-Lin Wan

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/28

摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.

摘要翻译： 描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。 在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如 由参考单元电路路径建立在感测电路比较器的参考输入端上。 一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。

公开(公告)号：US5955893A

公开(公告)日：1999-09-21

申请号：US767447

申请日：1996-12-16

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yin-Shang Liu

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yin-Shang Liu

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： An embodiment of the invention provides a buffer circuit having reduced power consumption. The buffer circuit comprises a power saving switch coupled to a buffer at a bias node. The buffer has an input that is adapted to receive input voltages at TTL levels, for example, and has an output adapted to provide output voltages at CMOS levels, for example. The power saving switch includes a level shifter and a voltage control circuit both coupled to the bias node. The output voltage of the buffer is fed back to the power saving switch. When the output voltage is at a low CMOS level, the power saving switch uses the voltage control circuit to provide a first bias voltage to the bias node. When the output voltage is at a high CMOS level, the power saving switch uses the level shifter to provide a second bias voltage to the bias node. The second bias voltage is chosen such that it prevents current flow between the bias node and the buffer at a predetermined input cutoff voltage. The level shifter provides a relatively constant second bias voltage by providing a relatively constant voltage shift V.sub.LS between a level shifter reference voltage V.sub.ref and the bias node. In the present embodiment, this voltage shift V.sub.LS is the absolute value of the gate to source threshold voltage of a FET. Accordingly, the second bias voltage is V.sub.ref -V.sub.LS. In one embodiment, the voltage control circuit includes a second level shifter to provide the first bias voltage.

摘要翻译： 本发明的实施例提供了具有降低的功耗的缓冲电路。 缓冲电路包括耦合到偏置节点处的缓冲器的省电开关。 例如，缓冲器具有适于以TTL电平接收输入电压的输入，并且具有适于在CMOS电平处提供输出电压的输出。 省电开关包括电平转换器和两个耦合到偏置节点的电压控制电路。 缓冲器的输出电压反馈给省电开关。 当输出电压处于低CMOS电平时，省电开关使用电压控制电路向偏置节点提供第一偏置电压。 当输出电压处于高CMOS电平时，省电开关使用电平移位器向偏置节点提供第二偏置电压。 第二偏置电压被选择为使得其在预定的输入截止电压下防止偏置节点和缓冲器之间的电流流动。 电平移位器通过在电平移位器参考电压Vref和偏置节点之间提供相对恒定的电压偏移VLS来提供相对恒定的第二偏置电压。 在本实施例中，该电压偏移VLS是FET的栅极 - 源极阈值电压的绝对值。 因此，第二偏置电压为Vref-VLS。 在一个实施例中，电压控制电路包括提供第一偏置电压的第二电平移位器。

公开(公告)号：US06188590B1

公开(公告)日：2001-02-13

申请号：US08860151

申请日：1997-06-17

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang

IPC分类号： H02M318

CPC分类号： H02M3/073 ,  H02M2003/076

摘要： The present invention discloses a regulator system (112) for regulating the output current and voltage (Vout) of a charge pump circuit (104). It is observed that the output current and voltage (Vout) of a charge pump circuit (104) can be regulated by varying the amplitude and frequency of a set of clock signals (modulated clocks). The present invention comprises means (decoders 1, 2; AM, FM units) for generating a set of control signals (VAD1-VFDn) as the function of the output current and voltage (Vout). The set of control signals (VAD1-VFDn) is coupled to a clock signal generation circuit (130) that generates a set of clock signals (modulated clocks) having a magnitude and a frequency depending on this set of at least one control signal. This set of clock signals (modulated clocks) is then used to drive the charge pump circuit (104). It is found that this regulator circuit (112) consumes less power than prior art regulator circuits.

摘要翻译： 本发明公开了一种用于调节电荷泵电路（104）的输出电流和电压（Vout）的调节器系统（112）。 观察到可以通过改变一组时钟信号（调制时钟）的幅度和频率来调节电荷泵电路（104）的输出电流和电压（Vout）。 本发明包括用于产生作为输出电流和电压（Vout）的函数的一组控制信号（VAD1-VFDn）的装置（解码器1,2，AM，FM单元）。 该组控制信号（VAD1-VFDn）耦合到时钟信号产生电路（130），该时钟信号产生电路产生具有取决于该组至少一个控制信号的幅度和频率的一组时钟信号（调制时钟）。 然后，该组时钟信号（调制时钟）用于驱动电荷泵电路（104）。 发现该调节器电路（112）比现有技术的调节器电路消耗更少的功率。

公开(公告)号：US6002630A

公开(公告)日：1999-12-14

申请号：US29945

申请日：1998-03-04

申请人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

发明人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

IPC分类号： G11C5/14 ,  G11C8/08 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C5/147

摘要： An on chip voltage generation circuit suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts) includes a sense circuit on the integrated circuit which generates an output indicating a level of the supply voltage. The on chip voltage supply circuit generates the on chip voltage in response to the output of the sense circuit and the supply voltage. The sense circuit output indicates the level of the supply voltage so that the on chip voltage supply circuit is able to adapt the amount of boosting utilized to produce the on chip voltage in response. The on chip voltage supply circuit generates the word line voltage at a node coupled to word line driving circuits in the device.

摘要翻译： PCT No.PCT / US97 / 21513 Sec。 371日期：1998年3月4日 102（e）1998年3月4日PCT PCT 1997年11月21日PCT公布。 公开号WO99 /​​ 27537 日期1999年6月3日适用于诸如具有低电源电压（例如2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路包括集成电路上的感测电路，其产生指示 电源电压。 片上电压供应电路响应于感测电路的输出和电源电压而产生片上电压。 感测电路输出表示电源电压的电平，使得片上电压供应电路能够适应用于产生片上电压的升压量。 片上电压供应电路在耦合到器件中的字线驱动电路的节点处产生字线电压。

公开(公告)号：US5818764A

公开(公告)日：1998-10-06

申请号：US796821

申请日：1997-02-06

申请人： Tom D. Yiu ,  I-Long Lee ,  Kuen-Long Chang ,  Han-Sung Chen ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Ray-Lin Wan

发明人： Tom D. Yiu ,  I-Long Lee ,  Kuen-Long Chang ,  Han-Sung Chen ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Ray-Lin Wan

IPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/16 ,  G11C16/00

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/16

摘要： A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.

摘要翻译： 提供电路，用于向浮动栅极存储单元阵列中的选定块的字线提供负的擦除电压。 该电路包括具有多个本地输出的电压电路，每个本地输出连接到浮动栅极存储器单元的相关块的字线。 块选择器电路耦合到电压电路的本地输出，并且选择性地切换每个本地输出以将擦除电压或非擦除电压施加到浮动栅极存储器单元的相关联块的字线上。 因此，对于在块擦除操作期间接收到较小负的非擦除电压的未选择块的字线，负字线应力减小。

公开(公告)号：US6147910A

公开(公告)日：2000-11-14

申请号：US386766

申请日：1999-08-31

申请人： Yu-Ming Hsu ,  Yin-Shang Liu ,  Chun-Hsiung Hung ,  Ray-Lin Wan ,  Y. T. Lin

发明人： Yu-Ming Hsu ,  Yin-Shang Liu ,  Chun-Hsiung Hung ,  Ray-Lin Wan ,  Y. T. Lin

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5624 ,  G11C2211/5642 ,  G11C7/1048

摘要： A page mode flash memory or floating gate memory device, including a page buffer based upon low current bit latches, and additional capabilities for parallel read and parallel program verify operations. The present device includes bit latch circuitry and/or method steps that facilitate such parallel operations and avoid data conflicts. Circuitry for separate read signals can serve to isolate the operations. Additionally, circuitry tied to the data verification signal can also be used. A diode type device can be used to isolate signal conditions that might indicate the cell does not need to be programmed. Bit-by-bit precharging of the bit lines can also be employed in order to save precharging power. Additionally, the large capacitance of the dataline might be used to delay discharging a particular dataline, and thereby allow a latch enabling signal to go high, thus eliminating the need for further isolation circuitry, or the like.

摘要翻译： 页面模式闪速存储器或浮动栅极存储器件，包括基于低电流位锁存器的页面缓冲器，以及用于并行读取和并行程序验证操作的附加功能。 本装置包括有利于这种并行操作并避免数据冲突的位锁存电路和/或方法步骤。 用于单独读取信号的电路可用于隔离操作。 此外，还可以使用与数据验证信号相关的电路。 可以使用二极管类型的器件来隔离可能指示电池不需要编程的信号条件。 为了节省预充电功率，也可以采用位线的逐位预充电。 此外，数据线的大电容可能用于延迟放电特定数据线，从而允许锁存使能信号变高，从而不需要进一步的隔离电路等。

公开(公告)号：US06255900B1

公开(公告)日：2001-07-03

申请号：US09284435

申请日：1999-04-12

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  Tien-Shin Ho ,  I-Long Lee ,  Tzeng-Hei Shiau ,  Ray-Lin Wan

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  Tien-Shin Ho ,  I-Long Lee ,  Tzeng-Hei Shiau ,  Ray-Lin Wan

IPC分类号： G05F110

CPC分类号： G11C16/30 ,  G05F3/242 ,  G11C5/145 ,  G11C16/08 ,  H02M3/07

摘要： An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.

摘要翻译： 提供了适用于具有低电源电压（例如，2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路。 电压升压电路耦合到电源电压输入和升压信号，该升压信号响应于升压信号的转变而升高集成电路上的节点上的片内电压。 升压电路具有第一模式，其响应于转换而以第一升压速率提升片上电压直到第一阈值，并且响应于转换的第二模式将片上电压提升到第二阈值 升压速率直到第二个阈值。 优选系统中的第二次升压速度比第一次升压速率慢。 检测电路耦合到接收片上电压的集成电路上的节点和电压升压电路。 当节点达到第一阈值时，检测电路向升压电路发信号，当节点达到第二阈值时，信号通知升压电路。 根据本发明的一个方面，在升压信号中的转变的小于5纳秒，更优选约2纳秒或更小的范围内达到第一阈值。

公开(公告)号：US06281719B1

公开(公告)日：2001-08-28

申请号：US09431346

申请日：1999-10-29

申请人： Tien-Shin Ho ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  I-Long Lee ,  Ray Lin Wan

发明人： Tien-Shin Ho ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  I-Long Lee ,  Ray Lin Wan

IPC分类号： H03B100

CPC分类号： H03K19/01728 ,  H03K19/00315

摘要： An output driver for an integrated circuit performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driver, and independent of the level of the data signal to be driven. A sense circuit senses an initial state of the output pad, before the output signal is supplied to the output pad, which indicates whether a voltage level on the output pad is above a threshold or below the threshold. A precharge circuit includes a pull up circuit and a pull down circuit. The pull up circuit is responsive to the initial state indicating that the voltage level on the output is below the threshold, and the pull down circuit is responsive to the initial state indicating that the voltage level on the output is above the threshold. A detector is coupled to the output, and produces a control signal indicating when output is near the threshold. Logic is responsive to the control signal from the detector to turn off the precharge circuit when the threshold is reached.

摘要翻译： 用于集成电路的输出驱动器在内部数据可用之前执行预充电功能，从而最小化这种数据的访问时间。 此外，预充电功能中使用的上拉和下拉电路与输出驱动器分离，并且与要驱动的数据信号的电平无关。 在输出信号被提供给输出焊盘之前，感测电路感测输出焊盘的初始状态，其指示输出焊盘上的电压电平是否高于阈值或低于阈值。 预充电电路包括上拉电路和下拉电路。 上拉电路响应于初始状态，指示输出上的电压电平低于阈值，并且下拉电路响应于初始状态，指示输出上的电压电平高于阈值。 检测器耦合到输出端，产生一个控制信号，指示何时输出接近阈值。 当达到阈值时，逻辑响应来自检测器的控制信号以关闭预充电电路。