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68 条记录 (耗时 0.035 秒)

    Reverse construction memory cell
    44.
    发明申请
    Reverse construction memory cell 有权
    反向构建记忆单元

    公开(公告)号：US20070023805A1

    公开(公告)日：2007-02-01

    申请号：US11189945

    申请日：2005-07-26

    申请人： David Wells ,  H. Manning

    发明人： David Wells ,  H. Manning

    IPC分类号： H01L29/76

    CPC分类号： H01L27/10885 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/10876 ,  H01L27/10882

    摘要： A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

    摘要翻译： 制造存储单元的方法包括在载体衬底上形成多个掺杂半导体层。 该方法还包括形成由绝缘材料隔开的多个数字线。 数字线排列在掺杂半导体层之上。 该方法还包括将多个沟槽蚀刻到掺杂半导体层中。 该方法还包括将绝缘材料沉积到多个沟槽中以形成多个电隔离的晶体管柱。 该方法还包括将形成在载体衬底上的结构的至少一部分结合到主体衬底。 该方法还包括从载体衬底分离载体衬底。

    Method and apparatus for adjusting feature size and position
    46.
    发明申请
    Method and apparatus for adjusting feature size and position 有权
    调整特征尺寸和位置的方法和装置

    公开(公告)号：US20060281266A1

    公开(公告)日：2006-12-14

    申请号：US11150408

    申请日：2005-06-09

    申请人： David Wells

    发明人： David Wells

    IPC分类号： H01L21/4763 ,  H01L21/336

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76838 ,  H01L27/105 ,  Y10S438/946 ,  Y10S438/947

    摘要： Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sideswalls. The critical dimension of the spacers is selected based upon the sidewall positions, so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers, with the critical dimensions of the second set of spacers chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set is used as a mask for etching a substrate. By selecting the critical dimensions of spacers based partly on the measured position of mandrels, the pitch of the spacers can be finely controlled.

    摘要翻译： 通过分开形成至少两组间隔物来最小化使用间距倍增形成的特征的间距的变化。 形成心轴并测量其侧壁的位置。 第一组间隔件形成在侧壁上。 基于侧壁位置选择间隔物的临界尺寸，使得间隔件居中在期望的位置。 去除心轴，并且间隔件用作后续间隔物形成的心轴。 然后将第二材料沉积在第一组间隔物上，其中第二组间隔物的临界尺寸选择为使得这些间隔物也位于其所需位置的中心。 去除第一组间隔物，将第二组用作蚀刻基底的掩模。 通过部分地基于心轴的测量位置选择间隔物的临界尺寸，可以精细地控制间隔物的间距。

    Memory array buried digit line
    47.
    发明申请
    Memory array buried digit line 有权

    公开(公告)号：US20060258119A1

    公开(公告)日：2006-11-16

    申请号：US11491461

    申请日：2006-07-21

    申请人： David Wells

    发明人： David Wells

    IPC分类号： H01L21/76 ,  H01L21/31

    CPC分类号： H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

    摘要： A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

    Memory array buried digit line
    48.
    发明申请
    Memory array buried digit line 有权

    公开(公告)号：US20060258118A1

    公开(公告)日：2006-11-16

    申请号：US11490619

    申请日：2006-07-21

    申请人： David Wells

    发明人： David Wells

    IPC分类号： H01L21/76 ,  H01L21/31

    CPC分类号： H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

    摘要： A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

    Apex split seal
    49.
    发明申请
    Apex split seal 失效
    Apex分割密封

    公开(公告)号：US20050180874A1

    公开(公告)日：2005-08-18

    申请号：US10882693

    申请日：2004-06-29

    申请人： David Wells

    发明人： David Wells

    IPC分类号： F01C1/02 ,  F01C1/063 ,  F01C19/00 ,  F01C19/04 ,  F04C27/00

    CPC分类号： F01C19/04

    摘要： A rotary machine including a rotor having apexes provided with apex seals achieves better efficiency through the use of apex split seals which minimize leakage across the apex seals to thereby allow operation at relatively high pressure values.

    摘要翻译： 包括具有顶点密封件的转子的旋转机器通过使用顶点分离密封件实现更好的效率，这使得密封顶端密封件的泄漏最小化，从而允许在相对高的压力值下运行。

    Semiconductive substrate processing methods and methods of processing a semiconductive substrate
    50.
    发明授权
    Semiconductive substrate processing methods and methods of processing a semiconductive substrate 失效
    半导体基板的加工方法和半导体基板的加工方法

    公开(公告)号：US06682873B2

    公开(公告)日：2004-01-27

    申请号：US10253550

    申请日：2002-09-23

    申请人： John Michiels ,  David Wells ,  Eric J. Knappenberger ,  James J. Alwan

    发明人： John Michiels ,  David Wells ,  Eric J. Knappenberger ,  James J. Alwan

    IPC分类号： G03C500

    CPC分类号： G03F7/00 ,  G03F7/0015 ,  H01J9/025 ,  H01J2329/00 ,  H01L21/0271 ,  H01L21/3081 ,  H01L21/31144 ,  Y10S430/15

    摘要： The present invention includes structures, lithographic mask forming solutions, mask forming methods, field emission display emitter mask forming methods, and methods of forming plural field emission display emitters. One aspect of the present invention provides a mask forming method including forming a masking layer over a surface of a substrate; screen printing plural masking particles over a surface of the masking layer; and removing at least portions of the masking layer using the masking particles as a mask. Another aspect of the present invention provides a method of forming plural field emission display emitters. This method includes forming a masking layer over an emitter substrate; screen printing a plurality of masking particles over the masking layer; removing portions of the masking layer intermediate the screen printed masking particles to form a plurality of masking elements; removing the masking particles from the masking elements; and removing portions of the emitter substrate to form plural emitters.

    摘要翻译： 本发明包括结构，光刻掩模形成溶液，掩模形成方法，场致发射显示发射体掩模形成方法以及形成多场发射显示发射体的方法。 本发明的一个方面提供一种掩模形成方法，包括在衬底的表面上形成掩模层; 在掩模层的表面上方式印刷多个掩蔽粒子; 以及使用所述掩模颗粒作为掩模去除所述掩蔽层的至少一部分。 本发明的另一方面提供了一种形成多个场发射显示发射器的方法。 该方法包括在发射极基板上形成掩模层; 在掩模层上方丝网印刷多个掩模颗粒; 去除屏幕印刷掩模颗粒之间的掩模层的部分以形成多个掩模元件; 从掩蔽元件去除掩蔽粒子; 以及去除所述发射极基板的部分以形成多个发射极。