公开(公告)号：US20080308942A1

公开(公告)日：2008-12-18

申请号：US11761495

申请日：2007-06-12

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76865 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

摘要翻译： 包括其中具有金属布线的电介质层，从金属布线向下延伸的孔，在金属布线上方的金属盖层和位于金属盖层的一部分内的局部电介质盖的半导体布线结构 公开了与金属布线的接触和相关方法。 局部电介质盖表示在双镶嵌互连的金属布线中有意创造的弱点，其在管线中引起电迁移（EM）空隙，而不是在从金属布线向下延伸的通孔的底部。 由于线路中的临界空隙尺寸失效，特别是金属盖层（衬垫）冗余度，远远大于通孔失效，所以EM寿命可以显着提高。

公开(公告)号：US20080254624A1

公开(公告)日：2008-10-16

申请号：US11734958

申请日：2007-04-13

申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76849

摘要： A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap.

摘要翻译： 描述了形成用于互连结构的改进的金属帽的结构和方法。 该方法包括在第一绝缘层的上部形成互连特征; 在所述互连特征和所述第一绝缘层上方覆盖介电覆盖层; 在所述电介质覆盖层上沉积第二绝缘层; 蚀刻所述第二绝缘层的一部分以形成通孔开口，其中所述通孔开口暴露所述互连特征的一部分; 轰击互连特征的部分以在互连特征的一部分中定义测量特征; 蚀刻通孔测量特征，用于形成邻近互连特征和电介质覆盖层的底切区域; 沉积贵金属层，所述贵金属层填充通孔测量特征的底切区域以形成金属盖; 以及在所述金属盖上沉积金属层。

公开(公告)号：US20080128907A1

公开(公告)日：2008-06-05

申请号：US11565810

申请日：2006-12-01

申请人： Chih-Chao Yang ,  Ping-Chuan Wang

发明人： Chih-Chao Yang ,  Ping-Chuan Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods of making the same. The semiconductor structure includes an interconnect feature substantially filled with a conductive material and disposed within a first dielectric material, and a second dielectric material comprising a contact via over the interconnect feature. The semiconductor structure further includes a gouging feature in the conductive material and adjacent to the contact via, and a first liner material deposited substantially only on surfaces of the conductive material in the gouging feature.

摘要翻译： 半导体结构及其制作方法。 半导体结构包括基本上填充有导电材料并且设置在第一电介质材料内的互连特征，以及包括互连特征上的接触通孔的第二电介质材料。 半导体结构还包括在导电材料中并且邻近接触通孔的气泡特征，以及基本上仅在气刨特征中的导电材料的表面上沉积的第一衬里材料。

公开(公告)号：US20080111239A1

公开(公告)日：2008-05-15

申请号：US11560044

申请日：2006-11-15

申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76847 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.

摘要翻译： 提供了具有改进的电迁移（EM）可靠性的互连结构。 本发明的互连结构避免了通过将至少部分地在金属互连内部结合EM防止衬垫而由EM故障引起的电路死路。 在一个实施例中，提供了一种“U形”防EM衬垫，其与导电材料与电介质材料分离的扩散阻挡层相邻。 在另一个实施例中，空间位于“U形”EM防护衬垫和扩散阻挡层之间。 在另一个实施例中，提供了一个与扩散阻挡件相邻的水平EM衬垫。 在又一个实施例中，在水平EM衬垫和扩散阻挡层之间存在一个空间。

公开(公告)号：US07345305B2

公开(公告)日：2008-03-18

申请号：US11248719

申请日：2005-10-12

申请人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US20070205434A1

公开(公告)日：2007-09-06

申请号：US11744621

申请日：2007-05-04

申请人： Fernando Guarin ,  J. Hostetter ,  Stewart Rauch ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Fernando Guarin ,  J. Hostetter ,  Stewart Rauch ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01L29/70 ,  H01L21/8222

CPC分类号： H01L29/7304 ,  H01L29/7378

摘要： A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal or a spike anneal.

摘要翻译： 提供了一种用于回收由雪崩热载体引起的降解的方法，其包括使表现出雪崩降解的空闲双极晶体管经历热退火步骤，所述热退火步骤增加了晶体管的温度，从而恢复了双极晶体管的雪崩劣化。 在一个实施例中，退火源是自发热结构，其是与双极晶体管的发射极并排放置的含Si电阻器。 在恢复步骤期间，包括自发热结构的双极晶体管被置于空闲模式（即，没有偏压），并且来自单独电路的电流流过自热结构。 在本发明的另一个实施例中，退火步骤是在双极晶体管的周围提供高正向电流（围绕峰值fT电流或更大）的结果，同时在低于雪崩条件（V CB）的情况下运行 超过1 V）。 在上述条件下，可以回收约40％以上的降解。 在本发明的又一实施例中，热退火步骤可以包括快速热退火（RTA），炉退火，激光退火或尖峰退火。

公开(公告)号：US20060254053A1

公开(公告)日：2006-11-16

申请号：US10908392

申请日：2005-05-10

申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H05K3/02 ,  H01K3/10 ,  B24B1/00

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US20060073695A1

公开(公告)日：2006-04-06

申请号：US10711697

申请日：2004-09-30

申请人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

IPC分类号： H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.

摘要翻译： 通过使用牺牲层形成用于半导体结构的气体电介质结构的方法。 特别地，本发明的一个实施例包括在基板上的电介质层中形成用于半导体结构的开口; 在开口上沉积牺牲层; 在所述牺牲层上执行定向蚀刻以在所述开口上形成牺牲层侧壁; 在所述开口上沉积导电衬垫; 在开口中沉积金属; 平面化金属和导电衬垫; 去除牺牲层侧壁以形成空隙; 以及在所述空隙上沉积盖层以形成气体介电结构。 本发明易于在镶嵌线形成过程中实现，并提高结构稳定性。

公开(公告)号：US20050186689A1

公开(公告)日：2005-08-25

申请号：US10783462

申请日：2004-02-20

申请人： Ronald Filippi ,  Jason Gill ,  Vincent McGahay ,  Paul McLaughlin ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Jason Gill ,  Vincent McGahay ,  Paul McLaughlin ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66 ,  H01L23/544

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

公开(公告)号：US09331012B2

公开(公告)日：2016-05-03

申请号：US13414825

申请日：2012-03-08

申请人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01K3/10 ,  H01L23/522 ,  H01L23/528 ,  H04L9/32 ,  H05K1/02

CPC分类号： H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

摘要翻译： 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。