公开(公告)号：US20070269736A1

公开(公告)日：2007-11-22

申请号：US11383548

申请日：2006-05-16

申请人： James P. Bucchignano ,  Wu-Song S. Huang ,  Lidija Sekaric ,  Raman G. Viswanathan

发明人： James P. Bucchignano ,  Wu-Song S. Huang ,  Lidija Sekaric ,  Raman G. Viswanathan

IPC分类号： G03C1/00

CPC分类号： G03F7/0757 ,  G03F7/0045 ,  G03F7/0046

摘要： The present invention discloses a resist composition and a method of forming a material structure having a pattern containing features having a dimension of about 40 nm or less by using the inventive resist. The inventive resist comprises a polymer and a photoacid generator. The polymer of the present invention comprises pendant polar moieties, pendant fluoroalcohol moieties, and a backbone containing SiO moieties. In the present invention, at least a portion of the polar moieties are protected with acid labile moieties having a low activation energy. It is preferred that some, but not all, of the pendant fluoroalcohol moieties are protected with acid labile moieties having a low activation energy.

摘要翻译： 本发明公开了一种抗蚀剂组合物和通过使用本发明的抗蚀剂形成具有尺寸为约40nm或更小的特征的图案的材料结构的方法。 本发明的抗蚀剂包含聚合物和光致酸产生剂。 本发明的聚合物包括极性极性部分，侧基氟代醇部分和含有SiO部分的主链。 在本发明中，至少一部分极性部分被具有低活化能的酸不稳定部分保护。 优选一些而不是全部的侧链氟代醇部分被具有低活化能的酸不稳定部分保护。

公开(公告)号：US20130285126A1

公开(公告)日：2013-10-31

申请号：US13611900

申请日：2012-09-12

申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

IPC分类号： H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66772 ,  H01L29/785 ,  H01L29/78654

摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.

公开(公告)号：US08445948B2

公开(公告)日：2013-05-21

申请号：US12886139

申请日：2010-09-20

申请人： Nicholas C. M. Fuller ,  Sarunya Bangsaruntip ,  Guy Cohen ,  Sebastian U. Engelmann ,  Lidija Sekaric ,  Qingyun Yang ,  Ying Zhang

发明人： Nicholas C. M. Fuller ,  Sarunya Bangsaruntip ,  Guy Cohen ,  Sebastian U. Engelmann ,  Lidija Sekaric ,  Qingyun Yang ,  Ying Zhang

IPC分类号： H01L29/78

CPC分类号： H01L21/32137 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  Y10S977/762 ,  Y10S977/938

摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine-and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

摘要翻译： 提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。 在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。 使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。 在另一个实施例中，使用封装/钝化层。 在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

公开(公告)号：US20110186969A1

公开(公告)日：2011-08-04

申请号：US12699552

申请日：2010-02-03

申请人： Ali Afzali-Ardakani ,  Devendra K. Sadana ,  Lidija Sekaric

发明人： Ali Afzali-Ardakani ,  Devendra K. Sadana ,  Lidija Sekaric

IPC分类号： H01L29/06 ,  H01L21/22

CPC分类号： H01L21/228 ,  H01L21/22 ,  H01L29/06

摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 本发明的实施方案使用光敏自组装单层将基材的表面图案化成亲水和疏水区域，并且掺杂剂化合物的水溶液（或醇）沉积在基材表面上。 掺杂剂仅粘附在亲水区上。 在沉积之后，用非常薄的氧化层涂覆衬底以封盖化合物，并且衬底在高温下退火以将掺杂剂原子扩散到硅中并激活掺杂剂。 在一个实施例中，该方法包括提供包括氧化物表面的半导体衬底，将所述表面图案化成疏水和亲水区域，在衬底上沉积包括掺杂剂的化合物，其中掺杂剂粘附到亲水区域，并将掺杂剂扩散到 氧化物表面。

公开(公告)号：US20110006367A1

公开(公告)日：2011-01-13

申请号：US12886139

申请日：2010-09-20

申请人： Nicholas C.M. Fuller ,  Sarunya Bangsaruntip ,  Guy Cohen ,  Sebastian U. Engelmann ,  Lidija Sekaric ,  Qingyun Yang ,  Ying Zhang

发明人： Nicholas C.M. Fuller ,  Sarunya Bangsaruntip ,  Guy Cohen ,  Sebastian U. Engelmann ,  Lidija Sekaric ,  Qingyun Yang ,  Ying Zhang

IPC分类号： H01L27/12

CPC分类号： H01L21/32137 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  Y10S977/762 ,  Y10S977/938

摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

摘要翻译： 提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。 在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。 使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。 在另一个实施例中，使用封装/钝化层。 在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

公开(公告)号：US07816275B1

公开(公告)日：2010-10-19

申请号：US12417954

申请日：2009-04-03

申请人： Nicholas C. M. Fuller ,  Sarunya Bangsaruntip ,  Guy Cohen ,  Sebastian U. Engelmann ,  Lidija Sekaric ,  Qingyun Yang ,  Ying Zhang

发明人： Nicholas C. M. Fuller ,  Sarunya Bangsaruntip ,  Guy Cohen ,  Sebastian U. Engelmann ,  Lidija Sekaric ,  Qingyun Yang ,  Ying Zhang

IPC分类号： H01L21/00

CPC分类号： H01L21/32137 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  Y10S977/762 ,  Y10S977/938

摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

摘要翻译： 提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。 在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。 使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。 在另一个实施例中，使用封装/钝化层。 在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

公开(公告)号：US20100129925A1

公开(公告)日：2010-05-27

申请号：US12324219

申请日：2008-11-26

申请人： Ali Afzali-Ardakani ,  Lidija Sekaric ,  George S. Tulevski

发明人： Ali Afzali-Ardakani ,  Lidija Sekaric ,  George S. Tulevski

IPC分类号： G01N27/04 ,  H01L29/06 ,  H01L21/02

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y15/00 ,  G01N27/041 ,  H01L29/0673

摘要： A semiconductor nanowire is coated with a chemical coating layer that comprises a functional material which modulates the quantity of free charge carriers within the semiconductor nanowire. The outer surface of the chemical coating layer includes a chemical group that facilitates bonding with molecules to be detected through electrostatic forces. The bonding between the chemical coating layer and the molecules alters the electrical charge distribution in the chemical coating layer, which alters the amount of the free charge carriers and the conductivity in the semiconductor nanowire. The coated semiconductor nanowire may be employed as a chemical sensor for the type of chemicals that bonds with the functional material in the chemical coating layer. Detection of such chemicals may indicate pH of a solution, a vapor pressure of a reactive material in gas phase, and/or a concentration of a molecule in a solution.

摘要翻译： 半导体纳米线涂覆有化学涂层，其包含调节半导体纳米线内的自由电荷载体的量的功能材料。 化学被膜层的外表面包括有助于通过静电力与要检测的分子结合的化学基团。 化学涂层和分子之间的结合改变化学涂层中的电荷分布，其改变半导体纳米线中游离载流子的量和导电性。 涂覆的半导体纳米线可以用作化学传感器，用于与化学涂层中的功能材料结合的化学品类型。 这种化学物质的检测可以指示溶液的pH，气相中的反应物质的蒸汽压和/或溶液中分子的浓度。

公开(公告)号：US07399573B2

公开(公告)日：2008-07-15

申请号：US11552677

申请日：2006-10-25

申请人： Wu-Song S. Huang ,  Lidija Sekaric ,  James J. Bucchignano ,  David P. Klaus ,  Raman Viswanathan

发明人： Wu-Song S. Huang ,  Lidija Sekaric ,  James J. Bucchignano ,  David P. Klaus ,  Raman Viswanathan

IPC分类号： G03C7/075

CPC分类号： G03F7/0757 ,  G03F7/0045 ,  G03F7/40 ,  Y10S430/106

摘要： The negative resist compositions especially suitable for electron beam-based lithographic processes are obtained by using a polymeric component containing first silsesquioxane moieties functionalized with a first reactive group having a first crosslinking reactivity and a first dissolution rate in aqueous alkaline solutions, and second silsesquioxane moieties functionalized with a second reactive group having a second crosslinking reactivity and a second dissolution rate in aqueous alkaline solutions, said reactivities being different from one another and said dissolution rates being different from one another. These negative resists enable improved negative lithographic processes, especially in the context of mask-making and direct-write techniques using electron beam lithography. The negative resists are also useful more generally in methods of forming patterned material features and advantageously show reduced incidence of image collapse at smaller groundrules.

摘要翻译： 特别适用于基于电子束的平版印刷方法的负型抗蚀剂组合物通过使用含有第一倍半硅氧烷部分的聚合物组分获得，所述第一倍半硅氧烷部分用第一反应性基团官能化，所述第一反应性基团具有第一交联反应性和在碱性水溶液中的第一溶解速率，第二倍半硅氧烷部分官能化 具有第二反应性基团，在碱性水溶液中具有第二交联反应性和第二溶解速率，所述反应性彼此不同，并且所述溶解速率彼此不同。 这些负性抗蚀剂能够改善负光刻工艺，特别是在使用电子束光刻的掩模制作和直接写入技术的上下文中。 负型抗蚀剂在更形成图案化材料特征的方法中也更有用，并且有利地显示在较小的基底层上图像塌陷的发生率降低。

公开(公告)号：US09029132B2

公开(公告)日：2015-05-12

申请号：US12537063

申请日：2009-08-06

申请人： Marwan H. Khater ,  Tak H. Ning ,  Lidija Sekaric ,  Sufi Zafar

发明人： Marwan H. Khater ,  Tak H. Ning ,  Lidija Sekaric ,  Sufi Zafar

IPC分类号： C12M1/34 ,  G01N33/551 ,  G01N33/543 ,  B82Y10/00 ,  G01N27/327 ,  H01L29/78

CPC分类号： G01N33/54373 ,  B82Y10/00 ,  G01N27/3276 ,  G01N27/4145 ,  G01N33/543 ,  H01L29/785 ,  Y10S977/721 ,  Y10S977/92 ,  Y10S977/953

摘要： A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.

摘要翻译： 用于生物分子的传感器包括包含未掺杂硅的硅片; 与硅鳍片相邻的源极区域，源极区域包括重掺杂的硅; 与所述硅鳍片相邻的漏极区域，所述漏极区域包括掺杂类型的与所述源极区域相同的掺杂类型的重掺杂硅; 以及覆盖源极区域和漏极区域之间的硅鳍片的外部部分的栅极电介质层，所述栅极电介质包括多个抗体，所述多个抗体被配置为与所述生物分子结合，使得漏极电流流动 当生物分子与抗体结合时，在源区和漏区之间变化。

公开(公告)号：US08481413B2

公开(公告)日：2013-07-09

申请号：US12721727

申请日：2010-03-11

申请人： Ali Afzali-Ardakani ,  Damon B. Farmer ,  Lidija Sekaric

发明人： Ali Afzali-Ardakani ,  Damon B. Farmer ,  Lidija Sekaric

IPC分类号： H01L21/22

CPC分类号： H01L21/225 ,  H01L21/2254

摘要： A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.

摘要翻译： 公开了用于掺杂半导体衬底的方法和系统。 在一个实施方案中，该方法包括在半导体衬底上形成无磷的磷酸层，并且从磷酸层中扩散磷在衬底中以在其中形成活化的磷掺杂剂。 在一个实施例中，将半导体衬底浸入磷化合物的溶液中以在衬底上形成磷化合物层，并且将该层磷加工形成磷酸层。 在一个实施方案中，该处理可以包括水解磷化合物的层以形成磷酸层。 在一个实施例中，在磷酸层上形成氧化物覆盖层以形成封盖的基底。 封装的衬底可以退火以在衬底中扩散磷并形成活化的掺杂剂。