公开(公告)号：US20210408371A1

公开(公告)日：2021-12-30

申请号：US17468896

申请日：2021-09-08

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason JANESKY

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US20210280778A1

公开(公告)日：2021-09-09

申请号：US17317061

申请日：2021-05-11

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Kenneth SMITH ,  Moazzem HOSSAIN ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L43/02

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US20210118948A1

公开(公告)日：2021-04-22

申请号：US17134865

申请日：2020-12-28

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Thomas ANDRE ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US20200266235A1

公开(公告)日：2020-08-20

申请号：US16870099

申请日：2020-05-08

Applicant: Everspin Technologies, Inc.

Inventor： Jijun SUN ,  Sanjeev AGGARWAL ,  Han-Jong CHIA ,  Jon M. SLAUGHTER ,  Renu WHIG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  G11B5/39 ,  H01L43/10

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

公开(公告)号：US20200243761A1

公开(公告)日：2020-07-30

申请号：US16845405

申请日：2020-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Kerry Joseph NAGEL ,  Chaitanya MUDIVARTHI ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer. (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US20190334082A1

公开(公告)日：2019-10-31

申请号：US16508450

申请日：2019-07-11

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Sanjeev AGGARWAL ,  Kerry Joseph NAGEL

IPC: H01L43/12 ,  G11B5/84 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.

公开(公告)号：US20190067566A1

公开(公告)日：2019-02-28

申请号：US16108762

申请日：2018-08-22

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Sarin A. DESHPANDE

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

公开(公告)号：US20180375018A1

公开(公告)日：2018-12-27

申请号：US16050749

申请日：2018-07-31

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Kerry Joseph NAGEL ,  Chaitanya MUDIVARTHI ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US20180309051A1

公开(公告)日：2018-10-25

申请号：US15958444

申请日：2018-04-20

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Sanjeev AGGARWAL ,  Moazzem HOSSAIN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L21/022 ,  H01L21/02203 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.

公开(公告)号：US20160260895A1

公开(公告)日：2016-09-08

申请号：US15145515

申请日：2016-05-03

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H01L43/12 ,  G01R33/09 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。