公开(公告)号：US20070183230A1

公开(公告)日：2007-08-09

申请号：US11669400

申请日：2007-01-31

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/848 ,  G11C5/04 ,  G11C7/06

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract translation: 在具有分配给表示存储器结构的逻辑部分的指定的存储单元组的存储器模块中，具有冗余组存储器单元的存储器冗余电路; 以及与指定组和冗余组耦合的冗余控制器。 可以包括冗余解码器的冗余控制器响应于预先选择的存储器组条件（例如，“FAILED”存储器组条件）将冗余组分配给存储器结构的逻辑部分。 冗余控制器还可以包括可选择的开关，例如，可以对预先选择的存储器组条件进行编码的熔丝。 指定组的存储器单元和冗余组的存储器单元可以是存储器行，存储器列，存储器模块的预选部分，存储器模块的可选择部分，存储器模块或其组合。

公开(公告)号：US07173867B2

公开(公告)日：2007-02-06

申请号：US10824905

申请日：2004-04-15

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C29/848 ,  G11C5/04 ,  G11C7/06

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract translation: 在具有分配给表示存储器结构的逻辑部分的指定的存储单元组的存储器模块中，具有冗余组存储器单元的存储器冗余电路; 以及与指定组和冗余组耦合的冗余控制器。 可以包括冗余解码器的冗余控制器响应于预先选择的存储器组条件（例如，“FAILED”存储器组条件）将冗余组分配给存储器结构的逻辑部分。 冗余控制器还可以包括可选择的开关，例如，可以对预先选择的存储器组条件进行编码的熔丝。 指定组的存储器单元和冗余组的存储器单元可以是存储器行，存储器列，存储器模块的预选部分，存储器模块的可选择部分，存储器模块或其组合。

公开(公告)号：US07095248B2

公开(公告)日：2006-08-22

申请号：US10939679

申请日：2004-09-13

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: H03K19/173

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software modes, is used with the plurality of memory cells to indicate that at least one memory cells is unusable and should be shifted out of operation. The software mode comprises a software programmable element adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware mode comprises a hardware element adapted to indicate the at least one memory cell is unusable and is gated with the software programmable element. The hardware and software modes act autonomously.

Abstract translation: 本发明涉及用于增加在单元阵列中使用的多个存储单元的制造成品率的系统和方法。 具有硬件和软件模式的可编程保险丝与多个存储器单元一起使用以指示至少一个存储器单元不可用并且应该被移出运行。 软件模式包括适于移动指示至少一个存储器单元有缺陷的适当值的软件可编程元件。 硬件模式包括适于指示至少一个存储器单元不可用并且被软件可编程元件选通的硬件元件。 硬件和软件模式自动运行。

公开(公告)号：US20060027733A1

公开(公告)日：2006-02-09

申请号：US11194580

申请日：2005-08-02

Applicant: Esin Terzioglu ,  Gil Winograd

Inventor： Esin Terzioglu ,  Gil Winograd

IPC: H01L27/00

CPC classification number: H04N5/361

Abstract: The present invention includes an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. In embodiments, the active pixel sensor can be implemented in a standard CMOS process, without the need for a specialized optical process. The active pixel sensor includes a reset FET, a photo-diode, a source follower, and a current source. The photo-diode is coupled to the source of the reset FET at a discharge node. The drain of the reset FET is couple to a power supply VDD. The discharge node is also coupled to the gate input of the source follower, the output of which is coupled to output node. In embodiments, shallow trench isolation is inserted between the active devices that constitute the photo-diode, the source follower, or the current source, where the shallow trench isolation reduces leakage current between these devices. As a result, dark current is reduced and overall sensitivity is improved. This enables the active pixel sensor to be integrated on a single substrate fabricated with conventional CMOS processing.

Abstract translation: 本发明包括有源像素传感器，其检测光能并产生与光能成比例的模拟输出。 在实施例中，有源像素传感器可以在标准CMOS工艺中实现，而不需要专门的光学工艺。 有源像素传感器包括复位FET，光电二极管，源极跟随器和电流源。 光电二极管在放电节点耦合到复位FET的源极。 复位FET的漏极耦合到电源VDD。 放电节点还耦合到源极跟随器的栅极输入，其输出耦合到输出节点。 在实施例中，浅沟槽隔离被插入在构成光电二极管，源极跟随器或电流源的有源器件之间，其中浅沟槽隔离减少了这些器件之间的漏电流。 结果，暗电流降低，整体灵敏度提高。 这使得有源像素传感器能够集成在用常规CMOS处理制造的单个衬底上。

公开(公告)号：US06990020B2

公开(公告)日：2006-01-24

申请号：US10984077

申请日：2004-11-08

Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Gil I. Winograd

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  G11C2216/10

Abstract: A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20–21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

Abstract translation: 非易失性存储单元（10）包括电荷存储节点（16）。 电绝缘的第一层（76）耦合在节点和第一电压源（22）之间。 电绝缘的第二层（66）耦合在节点和第二电压源（20-21）之间。 第一层的面积小于第二层的面积。 控制器（90）被布置成使得第一电压大于第二电压，使得从节点提取电荷并且被布置成使得第二电压大于第一电压，使得电荷被注入节点 。

公开(公告)号：US06947350B2

公开(公告)日：2005-09-20

申请号：US10712383

申请日：2003-11-12

Applicant: Gil I. Winograd ,  Esin Terzioglu ,  Ali Anvar ,  Sami Issa

Inventor： Gil I. Winograd ,  Esin Terzioglu ,  Ali Anvar ,  Sami Issa

IPC: G06F13/40 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/18 ,  G11C7/22 ,  G11C8/00 ,  G11C8/10 ,  G11C11/413 ,  G11C11/419 ,  G11C29/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848

Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier. One embodiment of the present invention relates to a memory device comprising a plurality of synchronous controlled global elements and a plurality of self-timed local elements. In this embodiment, at least one of the self-timed local elements interfaces with the synchronous controlled global element.

Abstract translation: 本发明涉及同步自定时存储装置。 该装置包括形成单元阵列的多个存储单元，与单元阵列接口的至少一个本地解码器，至少一个本地读出放大器和至少一个本地控制器。 本地感测放大器至少与解码器和单元阵列接口，并且适于对与其耦合的至少一条线进行预充电和均衡。 本地控制器与至少本地解码器和读出放大器的活动接口并进行协调。 本发明的一个实施例涉及包括多个同步受控全局元件和多个自定时局部元件的存储器件。 在该实施例中，自定时局部元件中的至少一个与同步控制的全局元件接口。

公开(公告)号：US06928026B2

公开(公告)日：2005-08-09

申请号：US10177311

申请日：2002-06-21

Applicant: Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

IPC: G06F13/40 ,  G11C5/06 ,  G11C7/10 ,  G11C7/18 ,  G11C7/22 ,  G11C8/00 ,  G11C8/10 ,  G11C11/413 ,  G11C11/419 ,  G11C29/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract translation: 本发明涉及用于处理存储器架构中的读写操作的系统和方法。 处理读和写操作的系统包括耦合到本地存储器块并且适于延长时钟脉冲的高部分的至少一个本地存储器块和同步控制的全局控制器。 用于处理读取和写入操作的方法包括使用与全局控制器接口的至少一个字线来扭曲时钟脉冲。

公开(公告)号：US20050122246A1

公开(公告)日：2005-06-09

申请号：US11042006

申请日：2005-01-25

Applicant: Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

Inventor： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

IPC: G11C7/06 ,  G11C7/14 ,  H03M1/12

CPC classification number: G11C7/065 ,  G11C7/14

Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

公开(公告)号：US06888778B2

公开(公告)日：2005-05-03

申请号：US10788204

申请日：2004-02-26

Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi

IPC: G11C7/06 ,  G11C8/00

CPC classification number: G11C7/06

Abstract: A decoder providing asynchronous reset, redundancy, or both, an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

Abstract translation: 提供异步复位，冗余或两者的解码器，具有冗余的异步可复位解码器。 解码器具有响应于时钟信号的同步部分; 与异步电路耦合的异步部分; 反馈复位部分，其响应于异步复位信号，基本上将同步部分与异步部分耦合并插入在同步部分之间; 信号输入; 与第一存储器单元组耦合的第一存储器输出; 与第二存储单元组耦合的第二存储器输出; 以及耦合在信号输入，第一存储器输出和第二存储器输出之间的选择器。 该解码器可以是面向行的存储器，并且因此提供具有行冗余的异步可重置行解码器，或者具有列冗余的异步可重置列解码器。

公开(公告)号：US06882591B2

公开(公告)日：2005-04-19

申请号：US10692230

申请日：2003-10-23

Applicant: Gil I. Winograd ,  Esin Terzioglu ,  Ali Anvar ,  Sami Issa

Inventor： Gil I. Winograd ,  Esin Terzioglu ,  Ali Anvar ,  Sami Issa

IPC: G06F13/40 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/18 ,  G11C7/22 ,  G11C8/00 ,  G11C8/10 ,  G11C11/413 ,  G11C11/419 ,  G11C29/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848

Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. One embodiment relates to a memory device comprising a muxing device and at least one cluster device coupled to the muxing device. Another embodiment comprises a method of performing at least one of a read and write operation in a memory device. The method comprises activating at least one cluster device in the memory device and firing at least one sense amp in the at least one cluster device.

Abstract translation: 本发明涉及同步自定时存储装置。 该装置包括形成单元阵列的多个存储单元，与单元阵列接口的至少一个本地解码器，至少一个本地读出放大器和至少一个本地控制器。 一个实施例涉及包括多路复用器件和耦合到复用器件的至少一个集群器件的存储器件。 另一个实施例包括执行存储器件中的读取和写入操作中的至少一个的方法。 该方法包括激活存储器设备中的至少一个集群设备并且激发至少一个集群设备中的至少一个感测放大器。