公开(公告)号：US06492228B2

公开(公告)日：2002-12-10

申请号：US09783581

申请日：2001-02-15

申请人： Fernando Gonzalez ,  Francis L Benistant

发明人： Fernando Gonzalez ,  Francis L Benistant

IPC分类号： H01L21336

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L29/66825 ,  H01L29/7887

摘要： A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.

摘要翻译： 公开了能够存储多位二进制数据的晶体管形式的闪存单元。 一对浮动门设置在控制门下方。 控制栅极连接到字线，而源极和漏极区域连接到相应的数字线。 浮动栅极通过控制施加到字线和数字线的电压而被单独充电和读出。 读出的电荷被解码为多位二进制值。 还公开了制造存储器单元并进行操作的方法。

公开(公告)号：US06486030B2

公开(公告)日：2002-11-26

申请号：US09810752

申请日：2001-03-15

申请人： Fernando Gonzalez ,  Chandra Mouli

发明人： Fernando Gonzalez ,  Chandra Mouli

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  Y10S257/915

摘要： The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material. Additionally, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.

摘要翻译： 本发明包括集成电路，其包括半导体材料衬底和由衬底支撑的第一场效应晶体管。 第一场效应晶体管包括第一晶体管栅极组件，其包括第一导电掺杂半导体材料层和仅一层导电氮化物。 集成电路还包括由衬底支撑的第二场效应晶体管。 第二场效应晶体管包括第二晶体管栅极组件，其包括导电掺杂半导体材料的第二层和至少两层导电氮化物。 本发明还包括场效应晶体管组件，其包括沟道区和沿着沟道区的绝缘材料。 晶体管组件还包括靠近沟道区的栅极堆叠。 栅极堆叠包括通过绝缘材料与沟道区分离的第一导电氮化物层。 堆叠还包括靠近第一导电氮化物层的导电掺杂半导体材料，以及通过导电掺杂的半导体材料与第一导电氮化物层分离的第二导电氮化物层。 此外，本发明包括形成场效应晶体管的方法以及形成集成电路的方法。

公开(公告)号：US06479875B1

公开(公告)日：2002-11-12

申请号：US09628527

申请日：2000-07-31

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L2976

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/3221 ,  Y10S148/06 ,  Y10S257/913

摘要： The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures. Following implantation and formation of the gettering structures, thermal processing may be carried out in order to induce lateral spread or widening of each of the gettering structures. In some embodiments, it may be desirable that each gettering structure substantially contact an adjacent gettering structure, which may be accomplished by directional ion implantation. In another embodiment of the present invention, a dual implantation is carried out. The shallow implantation migrates during thermal processing to fill crystal originated particles or pits (COPs) within the semiconductive substrate.

摘要翻译： 本发明涉及通过半导体衬底中的凹槽的离子注入在半导体衬底内形成多个吸气结构。 本发明的优选实施例包括通过使用反应性各向异性蚀刻介质形成凹陷，然后注入吸气材料。 通过改变反应性各向异性蚀刻介质的吸气材料来植入吸气材料。 本发明的方法的优点在于形成吸气结构，而不需要额外的掩蔽程序的成本，而不需要MeV植入设备和程序的费用。 结果，金属污染物将不会在靠近吸气结构的有源区域的区域中自由地移动通过半导体衬底。 在植入和形成吸气结构之后，可以进行热处理以引起每个吸气结构的横向扩展或扩大。 在一些实施例中，可能需要每个吸气结构基本上接触相邻的吸气结构，其可以通过定向离子注入来实现。 在本发明的另一个实施例中，进行双重植入。 浅加工在热处理期间迁移以填充半导体衬底内的晶体起始颗粒或凹坑（COP）。

公开(公告)号：US06448603B2

公开(公告)日：2002-09-10

申请号：US09738413

申请日：2000-12-13

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L27108

CPC分类号： H01L27/10852

摘要： An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an anive area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region. The contact region has a first segment adjacent to the gate electrode and a second segment interposed between the first segment and the field oxide region. The first segment is thereby isolated from the field oxide region by the second segment. The first segment is doped to a second conductivity type. A layer of storage polysilicon is formed in electrical contact with the first segment of the contact region but not the second segment of the contact region. The storage polysilicon is isolated from the field oxide through an insulating layer interposed between the storage polysilicon and the second segment of the contact region.

摘要翻译： 半导体衬底中的掺杂有源区和多晶硅上层之间的改进的存储节点结，诸如DRAM存储单元中的存储节点结。 存储节点结的面积和周长显着减小，并且结点从相邻隔离结构移开。 结合新结的示例性半导体器件包括在导电多晶硅层和半导体衬底上的有源区之间的存储节点结，衬底已经经过LOCOS步骤以产生由场氧化物区域界定的有源区。 绝缘栅电极形成在已经被掺杂到第一导电类型的衬底上的钝化区上。 包括有源区域的一部分的接触区域在栅电极的一侧和场氧化物区域之间横向延伸。 接触区域具有与栅电极相邻的第一段和介于第一段和场氧化物区之间的第二段。 因此，第一段由第二段与场氧化物区隔离。 第一段被掺杂到第二导电类型。 形成与接触区域的第一段电接触而不是接触区域的第二段的存储多晶硅层。 存储多晶硅通过介于存储多晶硅和接触区域的第二段之间的绝缘层与场氧化物隔离。

公开(公告)号：US06429449B1

公开(公告)日：2002-08-06

申请号：US09569992

申请日：2000-05-12

申请人： Fernando Gonzalez ,  Raymond A. Turi ,  Graham R. Wolstenholme ,  Charles L. Ingalls

发明人： Fernando Gonzalez ,  Raymond A. Turi ,  Graham R. Wolstenholme ,  Charles L. Ingalls

IPC分类号： H01L4700

CPC分类号： H01L27/24 ,  H01L27/1021

摘要： A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

摘要翻译： 用于将电流传送到存储器单元中的多状态存储器元件的垂直取向的二极管。 垂直二极管可以设置在从硅或氧化物层的顶部向下延伸的二极管容器中，并且可以由靠近二极管容器的内表面设置的硅和/或金属层的组合形成。 多状态存储元件可以由二极管上方的多态材料（例如硫族化物）形成以完成存储单元。

公开(公告)号：US06380103B2

公开(公告)日：2002-04-30

申请号：US09793248

申请日：2001-02-26

申请人： Fernando Gonzalez ,  Randhir P. S. Thakur

发明人： Fernando Gonzalez ,  Randhir P. S. Thakur

IPC分类号： H01L21306

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/31116 ,  H01L21/31662 ,  Y10S438/906 ,  Y10S438/913

摘要： At least both a rapid thermal etch step and a rapid thermal oxidation step are performed on a semiconductor substrate in situ in a rapid thermal processor. A method including an oxidation step followed by an etch step may be used to remove contamination and damage from a substrate. A method including a first etch step followed by an oxidation step and a second etch step may likewise be used to remove contamination and damage, and a final oxidation step may optionally be included to grow an oxide film. A method including an etch step followed by an oxidation step may also be used to grow an oxide film. Repeated alternate in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is accomplished.

摘要翻译： 在快速热处理器中至少在半导体衬底上进行快速热蚀刻步骤和快速热氧化步骤。 可以使用包括氧化步骤和随后的蚀刻步骤的方法来去除基底的污染和损伤。 同样可以使用包括第一蚀刻步骤之后的氧化步骤和第二蚀刻步骤的方法来去除污染物和损伤，并且可以任选地包括最终氧化步骤以生长氧化膜。 包括氧化步骤之后的蚀刻步骤的方法也可用于生长氧化膜。 可以使用重复的原位氧化和蚀刻步骤，直到完成所需的污染物或硅损伤去除。

公开(公告)号：US06376284B1

公开(公告)日：2002-04-23

申请号：US09570614

申请日：2000-05-12

申请人： Fernando Gonzalez ,  Gurtej S. Sandhu ,  Mike P. Violette

发明人： Fernando Gonzalez ,  Gurtej S. Sandhu ,  Mike P. Violette

IPC分类号： H01L2182

CPC分类号： H01L21/76804 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material. In a method of a second embodiment diodes are formed, each having a maximum width equal to f, which is equal to the minimum photolithographic limit of the photolithographic equipment being used, and distanced one from the other along a length of the digit line by a maximum distance equal to f; at least portions of the diodes are masked; at least a portion of an insulative material interposed between two diodes is removed to expose the buried digit line; and the conductive plug is formed in contact with the exposed portion of the buried digit line. After the formation of a programmable resistor in series with the diode a wordline is formed in electrical communication with each of the programmable resistors, and an insulative layer is formed overlying each wordline. Next an insulative spacer layer is deposited and etched to expose the conductive plug. The strapping layer is then formed overlying and in contact with the conductive plug.

摘要翻译： 一种存储器件，其中二极管串联连接到可编程电阻并与埋地数字线电连通。 导电插头电插入数字线和捆扎层之间，从而产生双金属方案，其中捆扎层是覆盖金属字线的第二金属层。 在第一实施例的方法中，捆扎材料通过覆盖在导电插塞上的平面着陆垫电连接到数字线。 绝缘材料倾斜到平面着陆垫，以提供有利于形成捆扎材料的表面。 在第二实施例的方法中，形成二极管，每个二极管具有等于f的最大宽度，其等于所使用的光刻设备的最小光刻极限，并且沿着数字线的长度彼此间隔一个 最大距离等于f; 二极管的至少部分被掩蔽; 插入在两个二极管之间的绝缘材料的至少一部分被去除以露出掩埋的数字线; 并且导电插塞形成为与掩埋的数字线的暴露部分接触。 在与二极管串联形成可编程电阻器之后，形成与每个可编程电阻器电连通的字线，并且在每个字线上形成绝缘层。 接下来，沉积和蚀刻绝缘间隔层以暴露导电插塞。 然后将捆扎层覆盖并与导电塞接触。

公开(公告)号：US06323088B1

公开(公告)日：2001-11-27

申请号：US09650078

申请日：2000-08-29

申请人： Fernando Gonzalez ,  Francis L. Bensistant

发明人： Fernando Gonzalez ,  Francis L. Bensistant

IPC分类号： H01L21336

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L29/66825 ,  H01L29/7887

摘要： A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while active doped regions (source and drain regions) are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. One or both of the floating gates has a side insulator which connects through a conductor to an associated active doped region thereby forming a capacitor across the side insulator between the floating gate. This capacitor and active region facilitates operation of the transistor as a flash memory cell. Methods of fabricating the memory cell and operating it are also disclosed.

公开(公告)号：US06287937B1

公开(公告)日：2001-09-11

申请号：US09619777

申请日：2000-07-20

申请人： Roger Lee ,  Fernando Gonzalez

发明人： Roger Lee ,  Fernando Gonzalez

IPC分类号： H01L2176

CPC分类号： H01L21/76237

摘要： The present invention relates to a well-drive process in which the process of well driving is carried out simultaneously with a densification cycle. The inventive method is particularly applicable to isolation trenches having widths at or below about 0.2 microns. The inventive method may be applied to other semiconductive structures of varying geometries.

摘要翻译： 本发明涉及一种井驱动方法，其中井致动过程与致密化循环同时进行。 本发明的方法特别适用于具有等于或小于约0.2微米的宽度的隔离沟槽。 本发明的方法可以应用于不同几何形状的其他半导体结构。

公开(公告)号：US06277731B1

公开(公告)日：2001-08-21

申请号：US09584256

申请日：2000-05-31

申请人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

发明人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

IPC分类号： H01L214763

CPC分类号： H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

摘要翻译： 形成连接的方法包括沉积下导体的步骤。 电介质层沉积在下导体上，电介质层具有与下导体相邻的下表面，并具有上表面。 形成在电介质层的上表面和下表面之间延伸的开口。 导电插塞沉积在开口内，插头具有接近电介质层的上表面的上表面。 上表面具有插头的上表面与电介质层相邻的边缘。 在插头的上表面的边缘附近形成凹部，凹部延伸到插塞和介电层两者中。 最后，在电介质层的上表面和插头的上表面上沉积上导体。 还公开了如此形成的连接。