公开(公告)号：US09864831B2

公开(公告)日：2018-01-09

申请号：US15071890

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Guido Ueberreiter ,  Lloyd C. Litt ,  Paul Ackmann

IPC: G06F17/00 ,  G06F17/50 ,  G03F1/36 ,  G03F7/20 ,  G03F1/68

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

公开(公告)号：US09817940B2

公开(公告)日：2017-11-14

申请号：US15585972

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

公开(公告)号：US09658531B2

公开(公告)日：2017-05-23

申请号：US14475967

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Guoxiang Ning ,  Chunyu Wong ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC: G03F1/26 ,  G03F7/20 ,  G03F1/28 ,  G03F1/50 ,  G03F1/42

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

公开(公告)号：US20160328510A1

公开(公告)日：2016-11-10

申请号：US14703179

申请日：2015-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

Abstract translation: 一种方法包括接收包括多个层的集成电路的布局，选择一个层并提供一个或多个瓦片数值。 基于瓦片数值将集成电路的管芯区域划分为多个瓦片。 确定在布局的基础上，如果瓦片中所选择的一个层的一部分具有用于包含测试单元或虚拟单元的可用空间，并且将指示结果的标签分配给 瓦。 根据所分配的标签确定是否满足一个或多个空间可用性标准，并且如果满足，则将标签用于在布局中放置一个或多个测试单元和一个或多个虚拟单元中的至少一个 。

公开(公告)号：US09252061B2

公开(公告)日：2016-02-02

申请号：US14243491

申请日：2014-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Chan Seob Cho ,  Paul Ackmann ,  Jung Yu Hsieh ,  Hui Peng Koh

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/306 ,  H01L27/088

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3212 ,  H01L22/12 ,  H01L27/088 ,  H01L29/4916 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

公开(公告)号：US09236301B2

公开(公告)日：2016-01-12

申请号：US13939322

申请日：2013-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Xiang Hu ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure.

Abstract translation: 通过（TSV）结构制造贯穿衬底通过以下方式促进：在衬底内形成至少一个应力缓冲液; 通过所述衬底内的接触形成贯通衬底，其中所述贯通衬底通孔结构和所述应力缓冲器被设置为彼此相邻或接触; 并且其中所述应力缓冲器包括配置或者被布置在相对于所述贯通基板通孔导体的位置处，至少部分地根据所述TSV结构是否是隔离的TSV结构，链接的TSV结构或 至少部分地基于TSV结构的类型来定义通过基于导体的贯穿衬底的应力缓冲器的应力缓解。