公开(公告)号：US09379209B2

公开(公告)日：2016-06-28

申请号：US14536167

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Jiajun Mao ,  Xusheng Wu ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/285 ,  H01L21/321 ,  H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/32053 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap.

Abstract translation: 包括导电金属栅电极的替代栅极结构形成在栅腔中，其中栅腔形成在形成在半导体器件的有源区上方的电介质材料中。 导电金属栅电极的上表面和电介质材料的上表面在公共平坦化工艺期间被平坦化，并且保护性导电帽选择性地形成在导电金属栅电极的平坦化上表面上并与之直接物理接触 。 接触结构形成在形成在替换栅极结构之上的电介质绝缘层中，接触结构直接接触保护性导电盖。

公开(公告)号：US20160133721A1

公开(公告)日：2016-05-12

申请号：US14536167

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Jiajun Mao ,  Xusheng Wu ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/32053 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap.

Abstract translation: 包括导电金属栅电极的替代栅极结构形成在栅腔中，其中栅腔形成在形成在半导体器件的有源区上方的电介质材料中。 导电金属栅电极的上表面和电介质材料的上表面在公共平坦化工艺期间被平坦化，并且保护性导电帽选择性地形成在导电金属栅电极的平坦化上表面上并与之直接物理接触 。 接触结构形成在形成在替换栅极结构之上的电介质绝缘层中，接触结构直接接触保护性导电盖。

公开(公告)号：US20160020275A1

公开(公告)日：2016-01-21

申请号：US14716696

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： HaoCheng Tsai ,  Min-hwa Chi

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76232 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/7846 ,  H01L29/7848

Abstract: Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.

Abstract translation: 本发明的实施例提供了一种改进的浅沟槽隔离结构和制造方法。 浅沟槽隔离腔包括具有西格玛腔形状的上部区域和具有基本矩形横截面的下部区域。 下部区域填充有具有良好间隙填充性能的第一材料。 西格玛腔填充有具有良好的应力诱导性能的第二材料。 在一些实施例中，可以消除源极/漏极应力源空穴，同时由浅沟槽隔离结构提供的应力。 在其他实施例中，来自浅沟槽隔离结构的应力可以用于补偿或抵消来自相邻晶体管的源极/漏极应力区域的应力。 这使得能够精确地调谐通道应力以实现晶体管的期望的载流子迁移率。

公开(公告)号：US20150255456A1

公开(公告)日：2015-09-10

申请号：US14195884

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/161 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: Embodiments herein provide approaches for forming a set of replacement fins in a semiconductor device. Specifically, a device is formed having a set of replacement fins over a substrate, each of the set of replacement fins comprising a first section separated from a second section by a liner layer, the first section having a lower dopant centration than a dopant concentration of the second section. In one embodiment, sequential epitaxial deposition with insitu doping is used to form the second section, the liner layer, and then the first section of each of the set of replacement fins. In another embodiment, the second section is formed over the substrate, and the liner layer is formed through a carbon implant. The first section is then epitaxially formed over the liner layer, and serves as the fin channel. As provided, upward dopant diffusion is suppressed, resulting in the first section of each fin being maintained with low doping so that the fin channel is fully depleted channel during device operation.

Abstract translation: 本文的实施例提供了在半导体器件中形成一组替换翅片的方法。 具体地说，在衬底上形成具有一组置换鳍片的器件，该组替换鳍片包括通过衬垫层与第二部分隔开的第一部分，第一部分具有比掺杂剂浓度低的掺杂剂浓度 第二部分。 在一个实施例中，使用具有内置掺杂的顺序外延沉积来形成第二部分，衬垫层，然后形成该组替换散热片中的每一个的第一部分。 在另一个实施例中，第二部分形成在衬底上，并且衬里层通过碳植入物形成。 然后第一部分外延地形成在衬里层上，并且用作鳍状通道。 如上所述，向上掺杂剂扩散被抑制，导致每个鳍片的第一部分被保持低掺杂，使得鳍片沟道在器件操作期间是完全耗尽的沟道。

公开(公告)号：US20150221726A1

公开(公告)日：2015-08-06

申请号：US14172362

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoong Shing Wong ,  Min-hwa Chi ,  Tae-Hoon Kim

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

Abstract translation: FinFET已经形成了与衬底电隔离的源极和漏极的外延结构。 有源区中的形状外延结构与源极和漏极区中的衬底分离，而沟道区中的形状外延结构保留。 由源极和漏极中的分离产生的间隙填充有电绝缘材料。 在填充间隙之前，可以减少由分离产生的缺陷。

公开(公告)号：US09087743B2

公开(公告)日：2015-07-21

申请号：US14084899

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L21/4763 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795

Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.

Abstract translation: 本发明的实施例提供一种半导体结构，其包括具有与多个鳍状物直接物理接触的外延半导体区域的finFET，其中外延半导体区域穿过绝缘体层并与半导体衬底直接物理接触。 finFET的栅极设置在诸如掩埋氧化物层的绝缘体层上。 还包括形成半导体结构的方法。

公开(公告)号：US09012986B2

公开(公告)日：2015-04-21

申请号：US14283881

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Werner Juengling

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7853

Abstract: A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

Abstract translation: 一种器件包括限定在基本上未掺杂的半导体材料层中的多个沟槽和鳍片，位于鳍片上并位于沟槽底部的栅极绝缘层，栅电极和器件隔离结构。 本文公开的一种方法包括识别多个翅片中的每一个的顶部宽度以及要形成在基本上未掺杂的半导体材料层中的多个沟槽的深度，其中，在操作期间，该装置适于在 至少三个可区分的条件，取决于施加到器件的电压，执行至少一个工艺操作以限定半导体材料层中的沟槽和鳍片，在鳍片上和沟槽的底部上形成栅极绝缘层并形成 在栅极绝缘层上方的栅电极。

公开(公告)号：US20150099336A1

公开(公告)日：2015-04-09

申请号：US14570049

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Hoong Shing Wong ,  Min-hwa Chi

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/823431 ,  H01L21/823821

Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region.

Abstract translation: 公开了具有外延形成的源极和漏极区域的FinFET结构的半导体集成电路的制造方法。 一种制造集成电路的方法包括在半导体衬底上形成多个硅鳍结构，在翅片结构上外延生长硅材料，其中在翅片结构上形成合并的源极/漏极区，并且各向异性地蚀刻至少一个 的合并源极漏极区域以形成未合并的源极/漏极区域。

公开(公告)号：US08815659B2

公开(公告)日：2014-08-26

申请号：US13716686

申请日：2012-12-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Nam Sung Kim

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.

Abstract translation: 形成FinFET器件的方法包括执行外延生长工艺以在半导体衬底上形成半导体材料层，其中半导体材料层的第一部分将成为FinFET器件的鳍结构，并且其中多个第二 半导体材料层的部分将成为FinFET器件的源极/漏极结构，在鳍状结构的至少一部分周围形成栅极绝缘层，并在栅极绝缘层的上方形成栅电极。

公开(公告)号：US08772117B2

公开(公告)日：2014-07-08

申请号：US13705261

申请日：2012-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Werner Juengling

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7853

Abstract: A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

Abstract translation: 一种器件包括限定在基本上未掺杂的半导体材料层中的多个沟槽和鳍片，位于鳍片上并位于沟槽底部的栅极绝缘层，栅电极和器件隔离结构。 本文公开的一种方法包括识别多个翅片中的每一个的顶部宽度以及要形成在基本上未掺杂的半导体材料层中的多个沟槽的深度，其中，在操作期间，该装置适于在 至少三个可区分的条件，取决于施加到器件的电压，执行至少一个工艺操作以限定半导体材料层中的沟槽和鳍片，在鳍片上和沟槽的底部上形成栅极绝缘层并形成 在栅极绝缘层上方的栅电极。