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    Patterning multiple, dense features in a semiconductor device using a memorization layer
    41.
    发明授权
    Patterning multiple, dense features in a semiconductor device using a memorization layer 有权
    使用记忆层在半导体器件中图形化多个密集特征

    公开(公告)号：US09224842B2

    公开(公告)日：2015-12-29

    申请号：US14258488

    申请日：2014-04-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

    IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

    Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

    Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

    SELF-ALIGNED VIA AND AIR GAP
    43.
    发明申请
    SELF-ALIGNED VIA AND AIR GAP 有权
    自对准通风和空气隙

    公开(公告)号：US20160260666A1

    公开(公告)日：2016-09-08

    申请号：US15155569

    申请日：2016-05-16

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Andy Chih-Hung Wei ,  Mark A. Zaleski

    IPC: H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/5329 ,  H01L29/0649

    Abstract: Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a first metal line beneath a second metal line within an ultra low-k (ULK) dielectric, the first metal line connected to the second metal line by a first via; a dielectric capping layer formed over the second metal line; a third metal line within first and second via openings formed within a ULK fill material formed over the dielectric capping layer, wherein the third metal line within the first via opening extends to a top surface of the dielectric capping layer, and wherein the third metal line within the second via opening is connected to the second metal by a second via passing through the dielectric capping layer; and an air gap formed between the third metal line within the first and seconds via openings.

    Abstract translation: 提供了用于在半导体器件内形成自对准通孔和气隙的方法。 具体地，一种方法产生一种器件，其具有：在超低k（ULK）电介质中的第二金属线下方的第一金属线，所述第一金属线通过第一通孔连接到所述第二金属线; 形成在所述第二金属线上的电介质覆盖层; 形成在形成在电介质覆盖层上的ULK填充材料内的第一和第二通孔内的第三金属线，其中第一通孔开口内的第三金属线延伸到介电覆盖层的顶表面，并且其中第三金属线 在第二通孔开口内通过穿过电介质盖层的第二通孔连接到第二金属; 以及形成在第一和第二通孔之间的第三金属线之间的气隙。

    BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION
    45.
    发明申请
    BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION 有权
    通过金属收缩双重积分的无边界接触形式

    公开(公告)号：US20160064514A1

    公开(公告)日：2016-03-03

    申请号：US14469014

    申请日：2014-08-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

    IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

    Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

    Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

    Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme
    47.
    发明授权
    Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme 有权
    Fin场效应晶体管（FinFET）器件使用单个间隔层形成，双重硬掩模方案

    公开(公告)号：US09159630B1

    公开(公告)日：2015-10-13

    申请号：US14330063

    申请日：2014-07-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Andy Chih-Hung Wei ,  Dae Geun Yang ,  Dae-han Choi

    IPC: H01L21/336 ,  H01L29/76 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823821 ,  H01L27/0924

    Abstract: Approaches for providing a single spacer, double hardmask dual-epi FinFET are disclosed. Specifically, at least one approach for providing the FinFET includes: forming a set of spacers along each sidewall of a plurality of fins of the FinFET device; forming a first ultra-thin hardmask over the plurality of fins; implanting the first ultra-thin hardmask over a first set of fins from the plurality of fins; removing the first ultra-thin hardmask over a second set of fins from the plurality of fins untreated by the implant; forming an epitaxial (epi) layer over the second set of fins; forming a second ultra-thin hardmask over the FinFET device; implanting the second ultra-thin hardmask; removing the second ultra-thin hardmask over the first set of fins; and growing an epi layer over the first set of fins.

    Abstract translation: 公开了用于提供单个间隔物，双重硬掩模双外延FinFET的方法。 具体地，用于提供FinFET的至少一种方法包括：沿着FinFET器件的多个鳍片的每个侧壁形成一组间隔物; 在所述多个翅片上形成第一超薄硬掩模; 将第一超薄硬掩模从多个翅片植入第一组翼片; 在未被植入物处理的多个翅片上从第二组翅片上移除第一超薄硬掩模; 在所述第二组翅片上形成外延（epi）层; 在FinFET器件上形成第二个超薄硬掩模; 植入第二超薄硬掩模; 在第一组翅片上移除第二超薄硬掩模; 并在第一组翅片上生长一个外延层。

    SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS
    49.
    发明申请
    SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS 有权
    用于集成电路的分立零电压电压场效应晶体管

    公开(公告)号：US20150270400A1

    公开(公告)日：2015-09-24

    申请号：US14217691

    申请日：2014-03-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar Singh ,  Konstantin G. Korablev ,  Andy Chih-Hung Wei

    IPC: H01L29/78 ,  H01L21/265 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

    Abstract: Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).

    Abstract translation: 提供了用于改变鳍式场效应晶体管（FinFET）器件中的阈值电压（例如，零阈值电压）的方法。 在本发明的实施例中，在具有p阱构造的翅片衬底上形成第一N +区和第二N +区。 位于第一N +区域和第二N +区域之间的翅片式衬底的区域掺杂有负极植入物种以形成n阱。 考虑到衬底装置的现有p-阱结构来改变该n阱区的尺寸和/或组成以改变FinFET器件的阈值电压（例如，产生零阈值电压FinFET器件）。

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