公开(公告)号：US20220181361A1

公开(公告)日：2022-06-09

申请号：US17113418

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy ,  Ramsey Hazbun

IPC: H01L27/144 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/18

Abstract: Structures including multiple photodiodes and methods of fabricating a structure including multiple photodiodes. A substrate has a first trench extending to a first depth into the substrate and a second trench extending to a second depth into the substrate that is greater than the first depth. A first photodiode includes a first light-absorbing layer containing a first material positioned in the first trench. A second photodiode includes a second light-absorbing layer containing a second material positioned in the second trench. The first material and the second material each include germanium.

公开(公告)号：US11322387B1

公开(公告)日：2022-05-03

申请号：US17069098

申请日：2020-10-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Brett T. Cucci

IPC: H01L27/00 ,  H01L21/76 ,  H01L21/26 ,  H01L27/06 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

公开(公告)号：US11315825B2

公开(公告)日：2022-04-26

申请号：US16553737

申请日：2019-08-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.

公开(公告)号：US11056382B2

公开(公告)日：2021-07-06

申请号：US15924444

申请日：2018-03-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L29/78 ,  H01L21/762 ,  H01L23/48 ,  H01L21/768

Abstract: Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.

公开(公告)号：US11029465B1

公开(公告)日：2021-06-08

申请号：US16832023

申请日：2020-03-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michal Rakowski ,  Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/28 ,  G02B6/293 ,  G02B6/02

Abstract: One illustrative device disclosed herein includes a micro-ring modulator that comprises an inner ring, an outer ring and a doped waveguide ring positioned between the inner ring and the outer ring. The device also includes an upper bus waveguide that is positioned vertically above at least a portion of the doped waveguide ring and at least a portion of the outer ring.

公开(公告)号：US12170313B2

公开(公告)日：2024-12-17

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20240243175A1

公开(公告)日：2024-07-18

申请号：US18098188

申请日：2023-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkata Narayana Rao Vanukuru ,  Steven M. Shank

IPC: H01L29/10 ,  H01L21/74 ,  H01L27/12

CPC classification number: H01L29/1087 ,  H01L21/743 ,  H01L27/1203

Abstract: Structures including a field-effect transistor field-effect and methods of forming a structure including a field-effect transistor. The structure comprises a trench isolation region in a substrate, and a body contact region that extends through the trench isolation region to the substrate. The structure further comprises a field-effect transistor including a gate connector, a first gate finger that extends from the gate connector, a second gate finger that extends from the gate connector, and a source/drain region disposed between the first gate finger and the second gate finger. The gate connector is positioned over the trench isolation region. The structure further comprises a gate contact coupled to the gate connector, and a body contact that penetrates through a portion of the gate connector to the body contact region.

公开(公告)号：US12027553B2

公开(公告)日：2024-07-02

申请号：US17896401

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Vibhor Jain ,  Alvin J. Joseph ,  Steven M. Shank

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

公开(公告)号：US11880065B2

公开(公告)日：2024-01-23

申请号：US17588470

申请日：2022-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Steven M. Shank ,  Takako Hirokawa

IPC: G02B6/12 ,  G02B6/13 ,  G02B6/293

CPC classification number: G02B6/12007 ,  G02B6/13 ,  G02B6/29338

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes an edge coupler having a longitudinal axis, a first ring resonator, and a second ring resonator. The first ring resonator has a first center point that is spaced from the longitudinal axis of the edge coupler by a first perpendicular distance. The second ring resonator has a second center point that is spaced from the longitudinal axis of the edge coupler by a second perpendicular distance.

公开(公告)号：US11822122B2

公开(公告)日：2023-11-21

申请号：US17462491

申请日：2021-08-31

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B1/00 ,  G02B6/122 ,  G02B6/125 ,  G02B6/12

CPC classification number: G02B6/1225 ,  G02B1/002 ,  G02B1/005 ,  G02B6/125 ,  G02B2006/1213 ,  G02B2006/12061 ,  G02B2006/12147

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.