公开(公告)号：US07999401B2

公开(公告)日：2011-08-16

申请号：US12178683

申请日：2008-07-24

申请人： Hideya Murai ,  Kentaro Mori ,  Shintaro Yamamichi ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

发明人： Hideya Murai ,  Kentaro Mori ,  Shintaro Yamamichi ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/544 ,  H01L23/5389 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  Y10T29/49146

摘要： Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.

摘要翻译： 半导体器件具有嵌入绝缘层中的半导体芯片。 半导体器件包括形成为具有外部连接焊盘的半导体芯片和用于通孔形成的定位标记; 包含非感光性树脂作为成分并具有多个通孔的绝缘层; 以及通过通路与外部连接焊盘电连接的布线，其至少一部分形成在绝缘层上。 绝缘层形成为在定位标记上方的部分具有凹部。 凹槽的底部是单独的绝缘层。 通孔相对于标记具有高位置精度。

公开(公告)号：US20110121445A1

公开(公告)日：2011-05-26

申请号：US13055372

申请日：2009-07-23

申请人： Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

发明人： Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/34 ,  H01L21/44

CPC分类号： H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/10674 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00

摘要： A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers.

摘要翻译： 半导体器件包括多个互连件，并且堆叠多个通孔。 半导体元件封装在绝缘层中。 提供在绝缘层中的至少一个通孔和/或设置在互连层中的至少一个互连件的横截面形状与在另一个绝缘层中提供的另一个绝缘层和/或互连中形成的通孔的截面形状不同 互连层之一。

公开(公告)号：US20100244231A1

公开(公告)日：2010-09-30

申请号：US12739302

申请日：2008-10-22

申请人： Shintaro Yamamichi ,  Kentaro Mori ,  Hideya Murai

发明人： Shintaro Yamamichi ,  Kentaro Mori ,  Hideya Murai

IPC分类号： H01L23/12 ,  H01L23/48

CPC分类号： H01L23/528 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.

摘要翻译： 半导体器件包括：半导体元件; 支撑基板，布置在所述半导体元件的与其表面相对的表面上，所述支撑基板设置有焊盘，所述支撑基板的面积比所述半导体元件宽; 在所述支撑基板上的掩埋绝缘层，用于将所述半导体元件埋入其中; 一个扇形互连从焊盘引出到掩埋绝缘层上的比半导体元件更外周的区域; 以及加强部，布置在半导体元件的外周的顶部的预设区域中，用于增加掩埋绝缘层的机械强度和扇出互连。

公开(公告)号：US08344498B2

公开(公告)日：2013-01-01

申请号：US12739302

申请日：2008-10-22

申请人： Shintaro Yamamichi ,  Kentaro Mori ,  Hideya Murai

发明人： Shintaro Yamamichi ,  Kentaro Mori ,  Hideya Murai

IPC分类号： H01L23/02

CPC分类号： H01L23/528 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.

摘要翻译： 半导体器件包括：半导体元件; 支撑基板，布置在所述半导体元件的与其表面相对的表面上，所述支撑基板设置有焊盘，所述支撑基板的面积比所述半导体元件宽; 在所述支撑基板上的掩埋绝缘层，用于将所述半导体元件埋入其中; 一个扇形互连从焊盘引出到掩埋绝缘层上的比半导体元件更外周的区域; 以及加强部，布置在半导体元件的外周的顶部的预设区域中，用于增加掩埋绝缘层的机械强度和扇出互连。

公开(公告)号：US20100314778A1

公开(公告)日：2010-12-16

申请号：US12867721

申请日：2009-02-06

申请人： Hideya Murai ,  Kentaro Mori ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima

发明人： Hideya Murai ,  Kentaro Mori ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L24/82 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/7688 ,  H01L23/5389 ,  H01L24/24 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/351 ,  H01L2924/00

摘要： In forming a semiconductor device, an insulation layer is formed on top of a semiconductor chip having a plurality of external terminals. A plurality of interconnections is formed on the insulating layer. External terminals are electrically connected to coordinated interconnections through a plurality of vias formed in the insulation layer. The interconnections are each formed integral with a via conduction part which covers the entire surfaces of the bottom and the sidewall sections of the via. The interconnection is formed so as to be narrower in its region overlying the via than the upper via diameter.

摘要翻译： 在形成半导体器件时，在具有多个外部端子的半导体芯片的顶部上形成绝缘层。 在绝缘层上形成多个互连。 外部端子通过形成在绝缘层中的多个通孔电连接到协调互连。 互连件与通孔导电部分形成一体，通孔导电部分覆盖通孔的底部和侧壁部分的整个表面。 互连形成为在其通孔上方的区域比上通孔直径更窄。

公开(公告)号：US08304915B2

公开(公告)日：2012-11-06

申请号：US13055372

申请日：2009-07-23

申请人： Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

发明人： Kentaro Mori ,  Hideya Murai ,  Shintaro Yamamichi ,  Masaya Kawano ,  Koji Soejima

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/10674 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00

摘要： A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers.

摘要翻译： 半导体器件包括多个互连件，并且堆叠多个通孔。 半导体元件封装在绝缘层中。 提供在绝缘层中的至少一个通孔和/或设置在互连层中的至少一个互连件的横截面形状与在另一个绝缘层中提供的另一个绝缘层和/或互连中形成的通孔的截面形状不同 互连层之一。

公开(公告)号：US06456352B1

公开(公告)日：2002-09-24

申请号：US09590285

申请日：2000-06-09

申请人： Hiroaki Matsuyama ,  Kazumi Kobayashi ,  Yoshihiko Hirai ,  Toshiya Ishii ,  Masayoshi Suzuki ,  Hideya Murai

发明人： Hiroaki Matsuyama ,  Kazumi Kobayashi ,  Yoshihiko Hirai ,  Toshiya Ishii ,  Masayoshi Suzuki ,  Hideya Murai

IPC分类号： G02F11343

CPC分类号： G02F1/133707 ,  G02F2201/121

摘要： A liquid crystal layer is sandwiched between two substrates of glass or the like and a gate terminal, a gate wiring, a control electrode and a drain terminal are arranged on the liquid crystal layer. The liquid crystal display device further has a control electrode terminal of the control electrode which is in an independent condition without crossing the gate wiring. A terminal part including this control electrode terminal and the gate terminal as well as the drain terminal is arranged on the outer side of the substrate panel. According to this construction, an arbitrary voltage can be applied to the control electrode so that the diagonal electrical field, which is necessary for the orientation division, can be set optimum in the intensity. Thereby the orientation division can be carried out properly. In addition, since there is no overlapping between the control electrode, including wiring and terminals, and the gate wiring, the short circuit problem can be alleviated to create good manufacturing yield of the liquid crystal display device.

摘要翻译： 液晶层夹在玻璃等的两个基板之间，在液晶层上设置栅极端子，栅极布线，控制电极和漏极端子。 液晶显示装置还具有控制电极的控制电极端子，该控制电极端子处于独立状态而不与栅极布线交叉。 包括该控制电极端子和栅极端子以及漏极端子的端子部分配置在基板面板的外侧。 根据该结构，可以对控制电极施加任意电压，使得可以将强度中的取向分割所必需的对角电场设定为最佳。 由此，可以适当地进行取向分割。 此外，由于在包括布线和端子的控制电极和栅极布线之间没有重叠，可以减轻短路问题，从而产生液晶显示装置的良好的制造成品率。

公开(公告)号：US06583839B2

公开(公告)日：2003-06-24

申请号：US08965619

申请日：1997-11-06

申请人： Teruaki Suzuki ,  Shinichi Nishida ,  Hideya Murai ,  Masayoshi Suzuki ,  Makoto Watanabe ,  Yoshihiko Hirai

发明人： Teruaki Suzuki ,  Shinichi Nishida ,  Hideya Murai ,  Masayoshi Suzuki ,  Makoto Watanabe ,  Yoshihiko Hirai

IPC分类号： G02F1343

CPC分类号： G02F1/134363 ,  G02F2001/133757 ,  G02F2201/122

摘要： An in-plane-switching liquid crystal display unit has a two-dimensional matrix of pixel regions each including a first auxiliary region and a second region. When no electric field is applied, liquid crystal molecules in the first and second regions are directed in respective orientations that lie at 90° with respect to each other. When a voltage is applied, the liquid crystal molecules are rotated in the same direction while maintaining their orientations in the first and second regions at 90° with respect to each other. Alternatively, the liquid crystal molecules in the first and second regions are directed in the same orientation when no electric field is applied, and when a voltage is applied, the liquid crystal molecules are rotated opposite directions while maintaining their orientations in symmetric relationship.

摘要翻译： 平面切换液晶显示单元具有各自包括第一辅助区域和第二区域的像素区域的二维矩阵。 当不施加电场时，第一和第二区域中的液晶分子相对于彼此相对于90°的各取向指向。 当施加电压时，液晶分子沿相同的方向旋转，同时保持它们在第一和第二区域中的取向相对于彼此成90°。 或者，当不施加电场时，第一和第二区域中的液晶分子以相同的取向被引导，并且当施加电压时，液晶分子沿相反方向旋转，同时保持它们的取向为对称关系。

公开(公告)号：US06466293B1

公开(公告)日：2002-10-15

申请号：US09643845

申请日：2000-08-23

申请人： Masayoshi Suzuki ,  Hideya Murai ,  Toshiya Ishii ,  Yoshihiko Hirai ,  Kazumi Kobayashi ,  Hiroaki Matsuyama ,  Daisuke Inoue

发明人： Masayoshi Suzuki ,  Hideya Murai ,  Toshiya Ishii ,  Yoshihiko Hirai ,  Kazumi Kobayashi ,  Hiroaki Matsuyama ,  Daisuke Inoue

IPC分类号： G02F11343

CPC分类号： G02F1/133753 ,  G02F1/133707 ,  G02F1/134336

摘要： This invention provide a liquid crystal display comprising a liquid crystal layer between two substrates each of which has an electrode, wherein the liquid crystal layer concomitantly has at least two micro-regions, and the electrode on one of the substrates has an opening, in the region of which there is provided a second electrode for controlling the initial orientation of the liquid crystal. The liquid crystal display has improved properties such as high contrast, quick response and excellent properties for an angle of visibility and can be manufactured without troublesome steps such as a photoresist step.

摘要翻译： 本发明提供了一种液晶显示器，其包括在两个基板之间的液晶层，每个液晶层具有电极，其中液晶层伴随地具有至少两个微区域，并且其中一个基板上的电极具有开口， 其区域设置有用于控制液晶的初始取向的第二电极。 液晶显示器具有改进的性能，例如高对比度，快速响应和对可视角度的优异性能，并且可以在没有诸如光致抗蚀剂步骤的麻烦的步骤的情况下制造。

公开(公告)号：US6115093A

公开(公告)日：2000-09-05

申请号：US49059

申请日：1998-03-27

申请人： Hideya Murai ,  Teruaki Suzuki ,  Masayoshi Suzuki

发明人： Hideya Murai ,  Teruaki Suzuki ,  Masayoshi Suzuki

IPC分类号： G02F1/1337 ,  G02F1/1343

CPC分类号： G02F1/134309 ,  G02F1/133753

摘要： To provide a liquid crystal display device easily produced having no disclination which causes a light leak, an excellent visual angle and an excellent contrast ratio, a liquid crystal layer is interposed between two substrates, two or more of micro areas coexist with each other in the liquid crystal layer, and liquid crystal molecules in the micro areas build up from a center of each pixel. A potential of a second electrode disposed on an opening is made approximately identical with that of a counter electrode, and a potential of a peripheral electrode is higher than that of the counter electrode, thereby obtaining the liquid crystal display device in which the liquid crystal molecules build up from the center of each pixel. Thus, the liquid crystal display device easily produced having a wide visual angle and an excellent contrast ratio is obtained. In addition, a polymer organic compound is dispersed in the liquid crystal to fix a built up direction of the liquid crystal molecules.

摘要翻译： 为了提供容易制造的液晶显示装置，其不会产生发生漏光的旋转，优异的视角和优异的对比度，液晶层插入在两个基板之间，两个或多个微区域彼此共存 液晶层和微区域中的液晶分子从每个像素的中心构成。 设置在开口上的第二电极的电位与对电极的电位大致相同，并且外围电极的电位高于对电极的电位，从而获得液晶分子 从每个像素的中心构建。 因此，获得容易制造的具有宽视角和优异对比度的液晶显示装置。 此外，聚合物有机化合物分散在液晶中以固定液晶分子的累积方向。