公开(公告)号：US20050263802A1

公开(公告)日：2005-12-01

申请号：US11129439

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。 低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。 包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

公开(公告)号：US06236790B1

公开(公告)日：2001-05-22

申请号：US09276494

申请日：1999-03-25

申请人： Naoki Okada ,  Hirohito Watanabe ,  Matsuhiro Miyamoto ,  Yoshiyasu Sato ,  Koichiro Watanabe ,  Hideyuki Iwata

发明人： Naoki Okada ,  Hirohito Watanabe ,  Matsuhiro Miyamoto ,  Yoshiyasu Sato ,  Koichiro Watanabe ,  Hideyuki Iwata

IPC分类号： G02B644

CPC分类号： G02B6/4433 ,  G02B6/4403 ,  G02B6/4411 ,  G02B6/448

摘要： There is provided an optical-fiber; and a cylinder body which is made from a cylindrically formed belt-shaped material and made of resin and which accommodates the optical-fiber therein.

摘要翻译： 提供光纤; 以及由圆柱形的带状材料制成并由树脂制成并且容纳其中的光纤的圆筒体。

公开(公告)号：US06225133B1

公开(公告)日：2001-05-01

申请号：US08299407

申请日：1994-09-01

申请人： Shintaro Yamamichi ,  Hirohito Watanabe ,  Yoichi Miyasaka

发明人： Shintaro Yamamichi ,  Hirohito Watanabe ,  Yoichi Miyasaka

IPC分类号： H01L2100

CPC分类号： H01L28/55 ,  H01L27/1085 ,  Y10T29/417 ,  Y10T29/43

摘要： After an interlayer insulating film is deposited on a silicon substrate, a contact hole or contact holes is or are formed at a desired position(s) and, then, after a polysilicon layer is deposited and the contact hole(s) is (are) embedded, the surface of the polysilicon layer is flattened by chemical and mechanical polishing using at least one of piperazine or colloidal silica slurry, and a barrier metal film 4 and a highly dielectric thin film 5 are deposited and processed to a desired size. Finally, an Al/TiN film 6 adapted for the upper electrode is formed. The leak current of the thin film capacitor which is obtained according to this method can be greatly reduced.

摘要翻译： 在硅衬底上沉积层间绝缘膜之后，在期望的位置形成或形成接触孔或接触孔，然后在沉积多晶硅层并且接触孔之后， 通过使用哌嗪或胶体二氧化硅浆料中的至少一种的化学和机械抛光使多晶硅层的表面平坦化，并且将阻挡金属膜4和高电介质薄膜5沉积并加工成所需的尺寸。 最后，形成适用于上电极的Al / TiN膜6。 根据该方法获得的薄膜电容器的漏电流可以大大降低。

公开(公告)号：US6054360A

公开(公告)日：2000-04-25

申请号：US869254

申请日：1997-06-04

申请人： Hirohito Watanabe

发明人： Hirohito Watanabe

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40

摘要： The method of manufacturing a semiconductor memory device with a stacked capacitor is disclosed. The method is featured by forming an insulating film on semiconductor substrate, forming a high melting point metal film interposed between capacitor electrode films, selectively etching the capacitor electrode films to expose at least a part of the high melting point metal film, and removing the high melting point metal film by etching using a solution containing at least one selected from sulfuric acid, nitric acid, hydrochloric acid, phosphoric acid, hydrogen peroxide, and ammonia. Thus only the high melting point metal film can be removed without etching the insulating film.

摘要翻译： 公开了一种制造具有堆叠电容器的半导体存储器件的方法。 该方法的特征在于在半导体衬底上形成绝缘膜，在电容器电极膜之间形成高熔点金属膜，选择性地蚀刻电容器电极膜以暴露至少一部分高熔点金属膜，并且去除高 通过使用含有选自硫酸，硝酸，盐酸，磷酸，过氧化氢和氨中的至少一种的溶液进行蚀刻的熔点金属膜。 因此，只有在不蚀刻绝缘膜的情况下才能除去高熔点金属膜。

公开(公告)号：US5989969A

公开(公告)日：1999-11-23

申请号：US926408

申请日：1997-09-08

申请人： Hirohito Watanabe ,  Ichiro Honma

发明人： Hirohito Watanabe ,  Ichiro Honma

IPC分类号： H01L21/285 ,  H01L21/02 ,  H01L21/205 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  H01L23/00 ,  H01L21/477

CPC分类号： H01L27/10852 ,  H01L27/11 ,  H01L27/1108 ,  H01L28/84

摘要： A method of forming a silicon layer disclosed herein includes the steps of depositing an amorphous silicon layer on a substrate, irradiating a silane gas to the substrate, and performing an annealing process in a high vacuum or in an inert gas. The amorphous silicon layer is thereby converted into a silicon layer having an uneven surface caused by hemispherical or spherical silicon grains. The annealing process may be performed while irradiating a hydrogen gas or an oxidizing gas. In this case, such a silicon layer that has an even surface is formed.

摘要翻译： 本文公开的形成硅层的方法包括以下步骤：在衬底上沉积非晶硅层，向衬底照射硅烷气体，并在高真空或惰性气体中进行退火处理。 从而将非晶硅层转变成由半球形或球形硅晶粒引起的具有不平坦表面的硅层。 可以在照射氢气或氧化气体的同时进行退火处理。 在这种情况下，形成具有均匀表面的硅层。

公开(公告)号：US5972750A

公开(公告)日：1999-10-26

申请号：US16952

申请日：1998-02-02

申请人： Hiroki Shirai ,  Taishi Kubota ,  Ichiro Honma ,  Hirohito Watanabe ,  Haruhiko Ono ,  Takeshi Okazawa

发明人： Hiroki Shirai ,  Taishi Kubota ,  Ichiro Honma ,  Hirohito Watanabe ,  Haruhiko Ono ,  Takeshi Okazawa

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/72

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883 ,  Y10S257/90

摘要： There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

摘要翻译： 公开了一种非易失性半导体存储器件，即使在不增加制造步骤数量的情况下，即使在微型化尺寸形成存储单元时也能够保持高电容比及其制造方法。 在具有掩埋扩散层型电池的闪速存储器中，源极区域和漏极区域形成为与其上表面具有突出和凹陷部分的多晶硅膜的多晶膜图案自对准地形成。

公开(公告)号：US5959326A

公开(公告)日：1999-09-28

申请号：US852530

申请日：1997-05-07

申请人： Fumiki Aiso ,  Hirohito Watanabe ,  Toshiyuki Hirota ,  Masanobu Zenke ,  Shuji Fujiwara

发明人： Fumiki Aiso ,  Hirohito Watanabe ,  Toshiyuki Hirota ,  Masanobu Zenke ,  Shuji Fujiwara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/205 ,  H01L21/283 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01G4/06

CPC分类号： H01L28/84

摘要： In a capacitor incorporated in a semiconductor device, a capacitor lower plate is formed of a first amorphous silicon film on an interlayer insulator film and a second amorphous silicon film stacked on the first amorphous silicon film. A crystallization preventing film is formed between the first and second amorphous silicon films, or alternatively, the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. A stacked structure formed of the first and second amorphous silicon films is patterned into a capacitor lower plate having a top surface and a side surface, and hemispherical grains are formed on not only the top surface but also the side surface of the patterned stacked structure. In this process, crystalline growth from the interlayer insulator film is prevented by the crystallization preventing film or by the fact that the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. Thus, concaves and convexes in the form of hemispherical grains are uniformly formed on not only the top surface but also the side surface of the patterned stacked structure, so that a remarkably increased capacitance can be obtained.

摘要翻译： 在并入半导体装置的电容器中，电容器下板由层叠绝缘膜上的第一非晶硅膜和层叠在第一非晶硅膜上的第二非晶硅膜形成。 在第一和第二非晶硅膜之间形成结晶防止膜，或者，形成第一非晶硅膜的杂质浓度低于第二非晶硅膜的杂质浓度。 由第一和第二非晶硅膜形成的堆叠结构被图案化成具有顶表面和侧表面的电容器底板，并且半球形晶粒不仅形成在图案化堆叠结构的顶表面而且形成在侧表面上。 在该方法中，通过防止结晶化膜或者形成第一非晶硅膜的杂质浓度低于第二非晶硅膜的杂质浓度来防止来自层间绝缘膜的晶体生长。 因此，半球状晶粒形式的凹凸不仅在图案化叠层结构的顶表面，而且均匀地形成，从而可以获得显着增加的电容。

公开(公告)号：US5837594A

公开(公告)日：1998-11-17

申请号：US868582

申请日：1997-06-04

申请人： Ichiroh Honma ,  Hirohito Watanabe

发明人： Ichiroh Honma ,  Hirohito Watanabe

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： Used nearer to a MOS transistor (25, 29(1), 29(2)) together with another capacitor electrode (39) with a dielectric film (37) interposed for use in a DRAM, a capacitor electrode is manufactured to include a conductor pole (53) and a tray-shaped conductor layer (55) which is held by the conductor pole and to include a plate portion (57) extended perpendicular to a pole axis and having a plate periphery and a peripheral portion (59) extended parallel to the pole axis from the plate periphery towards a pole end. Preferably, the tray-shaped conductor layer is held by the pole on a plurality of levels. A planar conductor layer may additionally be held at the pole end perpendicular to the pole axis. Word (41) and bit (49) lines are embedded in an insulator layer (43, 51) for the capacitor and the transistor.

摘要翻译： 使用更接近于MOS晶体管（25,29（1），29（2））的电容器电极（39）和具有插入用于DRAM的电介质膜（37）的电容器电极（39），制造电容器电极以包括导体 （53）和由导体极保持的托盘状导体层（55），并且包括垂直于极轴延伸的板部（57），并且具有板周边和平行延伸的周边部分（59） 从极板周边向极端延伸到极轴。 优选地，托盘状导体层由极保持在多个级上。 平面导体层可以另外保持在垂直于极轴的极端。 字（41）和位（49）线被嵌入用于电容器和晶体管的绝缘体层（43,41）中。

公开(公告)号：US5835337A

公开(公告)日：1998-11-10

申请号：US723274

申请日：1996-09-30

申请人： Hirohito Watanabe ,  Ichiroh Honma

发明人： Hirohito Watanabe ,  Ichiroh Honma

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01G4/30

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： In a semiconductor device, such as a memory cell, including a capacitor, a corrugated electrode is used as a lower electrode of the capacitor and is covered with an insulation film to be opposed to an upper electrode. The corrugated electrode is specified in section by a series of folded portions which are alternately folded vertically and horizontally. Practically, the corrugated electrode is formed by a corrugated wall which surrounds a hollow space and which has a rectangular or a polygonal shape on a plane. Alternatively, the corrugated wall has an irregular surface formed by an aggregation of grains so as to effectively widen a surface of the lower electrode. Such a corrugated electrode may be manufactured by a mold which is formed by selectively etching a stack of first-kind spacer films and second-kind spacer films.

公开(公告)号：US5661052A

公开(公告)日：1997-08-26

申请号：US617686

申请日：1996-03-19

申请人： Ken Inoue ,  Makoto Sekine ,  Hirohito Watanabe ,  Ichirou Honma

发明人： Ken Inoue ,  Makoto Sekine ,  Hirohito Watanabe ,  Ichirou Honma

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/283 ,  H01L21/335

CPC分类号： H01L29/665

摘要： The method of fabricating a semiconductor device, includes the steps of (a) forming gate oxides on regions separated by device isolation regions, (b) depositing an amorphous silicon or a polysilicon film, (c) depositing a removable space-forming film over the silicon film, (d) patterning the space-forming film and the silicon film into the same shape to form a gate electrode comprising the thus patterned space-forming film and silicon film, (e) depositing a silicon nitride film, (f) etching the silicon nitride film to form a first sidewall around a sidewall of the gate electrode, (g) depositing a silicon oxide film, (h) etching the silicon oxide film to form a second sidewall around and onto the first sidewall, (i) etching the space-forming film with hydrofluoric anhydride for removal so that the silicon film is exposed and the first sidewall remains unremoved, (j) forming source/drain regions, and (k) selectively depositing a refractory metal or metal silicide film on the silicon film and the source/drain regions. The method makes it easy to cause the first sidewall to have higher height than the amorphous or polysilicon film to thereby form low-resistance gate electrode and diffusion layers, resulting in that the gate electrode is not short-circuited with the diffusion layers.

摘要翻译： 制造半导体器件的方法包括以下步骤：（a）在由器件隔离区分离的区域上形成栅极氧化物，（b）沉积非晶硅或多晶硅膜，（c）在其上沉积可移除的空间形成膜 （d）将形成空间的膜和硅膜构图成相同的形状以形成包含如此构图的间隔形成膜和硅膜的栅电极，（e）沉积氮化硅膜，（f）蚀刻 所述氮化硅膜形成围绕所述栅电极的侧壁的第一侧壁，（g）沉积氧化硅膜，（h）蚀刻所述氧化硅膜以在所述第一侧壁周围形成第二侧壁，（i）蚀刻 用氢氟酸酐去除的空间形成膜，使得硅膜暴露，第一侧壁保持不被去除，（j）形成源/漏区，（k）在硅膜上选择性地沉积难熔金属或金属硅化物膜 和源极/漏极区域。 该方法容易使第一侧壁具有比非晶或多晶硅膜更高的高度，从而形成低电阻栅电极和扩散层，导致栅电极不与扩散层短路。