公开(公告)号：US20110298053A1

公开(公告)日：2011-12-08

申请号：US12997625

申请日：2010-09-19

申请人： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

发明人： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

IPC分类号： H01L29/78 ,  H01L21/3205 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L29/513 ,  H01L21/28176 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

摘要： A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.

摘要翻译： 具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边 门堆栈结构。 通过该方法制造的半导体器件。

公开(公告)号：US09012963B2

公开(公告)日：2015-04-21

申请号：US13501518

申请日：2011-11-18

申请人： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L29/49

CPC分类号： H01L29/78654 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.

摘要翻译： 本申请公开了一种半导体器件，其包括超薄半导体层中的源极区域和漏极区域; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极 由低Vt材料制成。 根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。 半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

公开(公告)号：US08859378B2

公开(公告)日：2014-10-14

申请号：US13377141

申请日：2011-08-10

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L27/1211 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66545

摘要： Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer; then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

摘要翻译： 本发明的实施例公开了一种制造Fin场效应晶体管的方法。 当形成翅片时，在翅片上形成跨鳍片的虚拟栅极，在虚拟栅极的侧壁上形成间隔物，并且在第一介电层上形成覆盖层，并在模拟栅极外部形成覆盖层， 间隔物 然后，通过间隔件在虚拟栅极的两侧形成自对准和升高的源极/漏极区域，其中栅极和源极/漏极区域的上表面在同一平面内。 栅极和源极/漏极区域的上表面位于相同的平面中，使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开，从而提高对准精度，解决接触插塞的不准确的对准以及提高器件AC性能。

公开(公告)号：US20140124847A1

公开(公告)日：2014-05-08

申请号：US14151441

申请日：2014-01-09

申请人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

发明人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.

摘要翻译： 公开了半导体装置及其制造方法。 一方面，该方法包括在衬底上形成第一屏蔽层，并且将第一屏蔽层作为掩模形成源区和漏区之一。 然后，在衬底上形成第二屏蔽层，并且用第二屏蔽层作为掩模形成源区和漏区中的另一个。 然后，去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。 最后，形成第一栅极电介质层，浮栅层和第二栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

公开(公告)号：US20140027864A1

公开(公告)日：2014-01-30

申请号：US13578872

申请日：2012-05-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

发明人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer.

摘要翻译： 公开了半导体装置及其制造方法。 在一个实施例中，该方法包括：在衬底上形成第一屏蔽层，并在第一屏蔽层的侧壁上形成第一间隔物; 用第一屏蔽层和第一间隔件作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 用第二屏蔽层和第一间隔物作为掩模形成源区和漏区中的另一个; 去除所述第一间隔物的至少一部分; 以及形成栅极电介质层，以及在所述第二屏蔽层的侧壁或所述第一间隔物的剩余部分的侧壁上形成间隔物形式的栅极导体。

公开(公告)号：US20120290998A1

公开(公告)日：2012-11-15

申请号：US13320291

申请日：2011-04-26

申请人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong ,  Meng Li

发明人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong ,  Meng Li

IPC分类号： G06F17/50

CPC分类号： H01L22/20

摘要： The present application discloses a device performance prediction method and a device structure optimization method. According to an embodiment of the present invention, a set of structural parameters and/or process parameters for a semiconductor device constitutes a parameter point in a parameter space, and a behavioral model library is established with respect to a plurality of discrete predetermined parameter points in the parameter space, and the predetermined parameter points being associated with their respective performance indicator values in the behavioral model library. The device performance prediction method comprises: inputting a parameter point, called “predicting point”, whose performance indicator value is to be predicted; and if the predicting point has a corresponding record in the behavioral model library, outputting the corresponding performance indicator value as a predicted performance indicator value of the predicting point, or otherwise if there is no record corresponding to the predicting point in the behavioral model library, calculating a predicted performance indicator value of the predicting point by interpolation based on Delaunay triangulation.

摘要翻译： 本申请公开了一种设备性能预测方法和设备结构优化方法。 根据本发明的实施例，用于半导体器件的一组结构参数和/或工艺参数构成参数空间中的参数点，并且针对多个离散的预定参数点建立行为模型库 参数空间以及与行为模型库中其各自的性能指标值相关联的预定参数点。 设备性能预测方法包括：输入要预测其性能指标值的称为预测点的参数点; 并且如果预测点在行为模型库中具有对应的记录，则输出相应的表现指标值作为预测点的预测性能指标值，否则如果没有与行为模型库中的预测点相对应的记录， 通过基于Delaunay三角测量的插值计算预测点的预测性能指标值。

公开(公告)号：US20120281468A1

公开(公告)日：2012-11-08

申请号：US13320331

申请日：2011-08-10

申请人： Qingqing Liang ,  Xiaodong Tong ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Xiaodong Tong ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： G11C11/34

CPC分类号： G11C11/39 ,  G11C17/06 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/1027

摘要： The present disclosure provides a semiconductor device and a semiconductor memory device. The semiconductor device can be used as a memory cell, and may comprise a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the semiconductor device by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the semiconductor device by applying a reverse bias, which is approaching to the reverse breakdown region of the semiconductor device, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the semiconductor device may be effectively used for data storage. The semiconductor memory device comprises an array of memory cells consisted of the semiconductor devices.

摘要翻译： 本公开提供了半导体器件和半导体存储器件。 半导体器件可以用作存储单元，并且可以包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。 第一数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来存储在半导体器件中。 第二数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加正在接近半导体器件的反向击穿区域的反向偏压来存储在半导体器件中。 以这种方式，半导体器件可以有效地用于数据存储。 半导体存储器件包括由半导体器件组成的存储器单元的阵列。

公开(公告)号：US20120261727A1

公开(公告)日：2012-10-18

申请号：US13380061

申请日：2011-02-27

申请人： Huicai Zhong ,  Qingqing Liang

发明人： Huicai Zhong ,  Qingqing Liang

IPC分类号： H01L29/772 ,  H01L21/768

CPC分类号： H01L29/78 ,  H01L21/76895 ,  H01L21/76897

摘要： A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.

摘要翻译： 提供半导体器件和用于制造半导体器件的局部互连结构的方法。 该方法包括在半导体衬底上的栅极的两侧上的侧壁间隔件和外侧壁间隔件之间形成可移除的牺牲侧壁间隔件，以及在侧壁间隔件和外侧壁之间的局部互连结构中的源极/漏极区域处形成接触通孔 在去除牺牲侧壁间隔物之后立即在栅极的同一侧上间隔开。 一旦源极/漏极通孔填充有导电材料以形成接触孔，接触孔的高度应与栅极的高度相同。 在本地互连结构中，建立后续的第一金属布线层和源极/漏极区域或较低电平的栅极区域之间的电连接的接触通孔应制成相同的深度。

公开(公告)号：US20120220097A1

公开(公告)日：2012-08-30

申请号：US13061824

申请日：2010-09-26

申请人： Huicai Zhong ,  Qingqing Liang

发明人： Huicai Zhong ,  Qingqing Liang

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area 220 is limited by forming an opening 214 between the first spacer 208 and the third spacer 212. The raised active area 220 is formed in the opening 214 in a self-aligned manner, so that a better profile of the raised active area 220 may be achieved and the possible shorts between adjacent devices caused by an unlimited manner may be avoided. Moreover, based on such a manufacturing method, it is easy to make the gate electrode 204 to be flushed with the raised active area 220, and is also easy to implement the dual stress nitride process so as to increase the mobility of the device.

摘要翻译： 提供一种制造半导体器件的方法，其中在形成栅极堆叠及其第一间隔物之后，形成第二间隔物和第三间隔物; 然后通过移除第二间隔件在第一间隔件和第三间隔件之间形成开口。 通过在第一间隔件208和第三间隔件212之间形成开口214来限制凸起的有效区域220的形成范围。凸起的有源区域220以自对准的方式形成在开口214中，使得 可以实现凸起的有效区域220的更好的轮廓，并且可以避免由无限制的方式引起的相邻设备之间的可能的短路。 此外，基于这样的制造方法，可以容易地利用凸起的有源区域220冲洗栅电极204，并且也容易实施双应力氮化物工艺，以增加器件的移动性。

公开(公告)号：US20120181509A1

公开(公告)日：2012-07-19

申请号：US13143932

申请日：2011-02-23

申请人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/775 ,  H01L21/335

CPC分类号： H01L29/66045 ,  H01L29/1606 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

摘要： A graphene device structure and a method for manufacturing the same are provided. The graphene device structure comprises: a graphene layer; a gate region formed on the graphene layer; and a doped semiconductor region formed at one side of the gate region and connected with the graphene layer, wherein the doped semiconductor region is a drain region of the graphene device structure, and the graphene layer formed at one side of the gate region is a source region of the graphene device structure. The on/off ratio of the graphene device structure may be improved by the doped semiconductor region without increasing the band gaps of the graphene material, so that the applicability of the graphene material in CMOS devices may be enhanced without decreasing the carrier mobility of graphene materials and speed of the devices.

摘要翻译： 提供石墨烯器件结构及其制造方法。 石墨烯器件结构包括：石墨烯层; 形成在所述石墨烯层上的栅极区域; 以及形成在所述栅极区域的一侧并与所述石墨烯层连接的掺杂半导体区域，其中所述掺杂半导体区域是所述石墨烯器件结构的漏极区域，并且形成在所述栅极区域一侧的所述石墨烯层是源极 石墨烯器件结构的区域。 可以通过掺杂半导体区域改善石墨烯器件结构的开/关比，而不增加石墨烯材料的带隙，从而可以增强石墨烯材料在CMOS器件中的适用性，而不降低石墨烯材料的载流子迁移率 和设备的速度。