公开(公告)号：US09727475B2

公开(公告)日：2017-08-08

申请号：US14497740

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Yen-Cheng Liu ,  Joseph Nuzman ,  Ashok Jagannathan ,  Bahaa Fahim ,  Nithiyanandan Bashyam

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0831

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F2212/452

Abstract: An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.

公开(公告)号：US09626321B2

公开(公告)日：2017-04-18

申请号：US14060191

申请日：2013-10-22

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/40 ,  G06F12/0831 ,  G06F13/42 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0815 ,  H04L12/741 ,  G06F9/44

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

公开(公告)号：US09575895B2

公开(公告)日：2017-02-21

申请号：US14609620

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Kenneth C. Creta ,  Sridhar Muthrasanallur ,  Bahaa Fahim

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/452 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。

公开(公告)号：US20150186191A1

公开(公告)日：2015-07-02

申请号：US14142137

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Bahaa Fahim ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

IPC: G06F9/52 ,  G06F12/08

CPC classification number: G06F9/524 ,  G06F12/0815 ,  G06F12/0855

Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.

Abstract translation: 这里公开了一种用于防止处理器中的死锁的缓存代理。 缓存代理包括被配置为从处理器的核心接收请求的接收器。 缓存代理包括耦合到接收器的入口逻辑，以确定请求潜在地是可缓存的请求。 入口逻辑是确定请求不会耗尽可用的一致性资源。 入口逻辑是允许响应于该请求不消耗可用的一致性资源的确定来处理该请求。

公开(公告)号：US20150143051A1

公开(公告)日：2015-05-21

申请号：US14609620

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Kenneth C. Creta ,  Sridhar Muthrasanallur ,  Bahaa Fahim

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/452 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。