公开(公告)号：US09692589B2

公开(公告)日：2017-06-27

申请号：US14866925

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Fulvio Spagna ,  Debendra Das Sharma

IPC: H04L7/027 ,  H04L25/20 ,  H04L1/24

CPC classification number: H04L1/241 ,  H04L1/243 ,  H04L25/20

Abstract: A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.

公开(公告)号：US20170109315A1

公开(公告)日：2017-04-20

申请号：US15393153

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert H. Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/42 ,  H04L9/06 ,  G06F11/10 ,  G06F13/40

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US09596108B2

公开(公告)日：2017-03-14

申请号：US14292743

申请日：2014-05-30

Applicant: INTEL CORPORATION

Inventor： Sitaraman V. Iyer ,  Fulvio Spagna

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03949 ,  H04L7/0062 ,  H04L25/03146

Abstract: Described is an apparatus which comprises: a Decision Feedback Equalizer (DFE); and a phase detector, operationally coupled to the DFE, to set a sampling phase based on a first post-cursor value of a composite pulse response being substantially equal to zero when the phase detector collects data bits having current bit and next bit such that value of the current bit is unequal to a value of the next bit.

Abstract translation: 描述了一种装置，其包括：判决反馈均衡器（DFE）; 以及相位检测器，可操作地耦合到DFE，当相位检测器收集具有当前位和下一位的数据位时，基于复合脉冲响应的第一后标值来设置采样相位，该第一后置光标值基本上等于零， 的当前位不等于下一位的值。

公开(公告)号：US20170019247A1

公开(公告)日：2017-01-19

申请号：US14866925

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Fulvio Spagna ,  Debendra Das Sharma

IPC: H04L7/027 ,  H04L1/24 ,  H04L25/20

CPC classification number: H04L1/241 ,  H04L1/243 ,  H04L25/20

Abstract: A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.

Abstract translation: 提供了一种转接器，其包括接收器，用于接收来自包括定义的二进制序列的一部分的第一设备的信号，漂移缓冲器，用于重新计算二进制序列，并且从二进制数提供种子到线性反馈移位寄存器（LFSR） 序列，LFSR从种子生成二进制序列的预期版本，以及模式检查逻辑，以将从第一设备接收的后续信号中的序列与由LFSR生成的二进制序列的预期版本进行比较。

公开(公告)号：US20160365866A1

公开(公告)日：2016-12-15

申请号：US15249120

申请日：2016-08-26

Applicant: INTEL CORPORATION

Inventor： Shenggao Li ,  Guluke Tong ,  Sujatha B. Gowder ,  Fulvio Spagna

IPC: H03L7/099 ,  H03L7/24 ,  H03L5/00

CPC classification number: H03L7/0991 ,  H03B5/00 ,  H03B5/1246 ,  H03B5/1278 ,  H03K3/0315 ,  H03L1/00 ,  H03L1/02 ,  H03L1/022 ,  H03L5/00 ,  H03L7/07 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18 ,  H03L7/24 ,  H03L2207/06

Abstract: Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). In embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.

Abstract translation: 实施例包括用于数字控制振荡器（DCO）的开环电压调节和漂移补偿的装置，方法和系统。 在实施例中，通信电路可以包括DCO，开环电压调节器和校准电路。 开环稳压器可以接收校准电压并且可以产生调节电压。 调节电压可以传递到DCO。 在校准模式期间，校准电路可以将调节电压与参考电压进行比较，并根据比较调节校准电压，以将调节电压提供给目标值。 在监视模式期间，校准电路可以接收用于调谐DCO的调谐码，并且基于调谐码的值进一步调整校准电压。