公开(公告)号：US10990155B2

公开(公告)日：2021-04-27

申请号：US16663658

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US20200012329A1

公开(公告)日：2020-01-09

申请号：US16546441

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US10474216B2

公开(公告)日：2019-11-12

申请号：US14971302

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Dorit Shapira ,  Itai Feit ,  Nadav Shulman ,  Efraim (Efi) Rotem ,  Tal Kuzi ,  Eliezer Weissmann ,  Tomer Ziv ,  Nir Rosenzweig

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

公开(公告)号：US10429919B2

公开(公告)日：2019-10-01

申请号：US15635307

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US10423202B2

公开(公告)日：2019-09-24

申请号：US15093042

申请日：2016-04-07

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Tod F. Schiff ,  Doron Rajwan ,  Jeffrey M. Jull ,  James G. Hermerding, II ,  Nir Rosenzweig ,  Maytal Toledano ,  Alexander B. Uan-Zo-Li

IPC: G06F1/26 ,  G08B21/18 ,  G06F1/3212 ,  G06F1/324 ,  G08B25/08

Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

公开(公告)号：US10281975B2

公开(公告)日：2019-05-07

申请号：US15190417

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  G06F1/3228 ,  G06F9/30

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US10268255B2

公开(公告)日：2019-04-23

申请号：US15197083

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Efraim Rotem ,  Alexander Gendler ,  Ankush Varma

IPC: G06F1/26 ,  G06F1/28 ,  G06F9/38 ,  G06F9/44 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/329

Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.

公开(公告)号：US10222851B2

公开(公告)日：2019-03-05

申请号：US15331051

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Gal Leibovich ,  Tomer Ziv ,  Amit Gabai ,  Jorge P. Rodriguez ,  Jeffrey A. Carlson

IPC: G06F1/32 ,  G06F1/324 ,  G05F1/10 ,  H03L7/08 ,  G06F1/28 ,  G06F1/3206

Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.

公开(公告)号：US10175740B2

公开(公告)日：2019-01-08

申请号：US15135682

申请日：2016-04-22

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Paul Diefenbaugh ,  Guy Therien ,  Nir Rosenzweig

IPC: G06F1/32

Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

公开(公告)号：US20180059748A1

公开(公告)日：2018-03-01

申请号：US15702970

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman ,  Tomer Ziv

IPC: G06F1/20 ,  G06F1/32 ,  G01K13/00

CPC classification number: G06F1/206 ,  G01K1/026 ,  G01K13/00 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F9/5094

Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.