公开(公告)号：US11749577B2

公开(公告)日：2023-09-05

申请号：US18089536

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49568 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/02371

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11735533B2

公开(公告)日：2023-08-22

申请号：US16437254

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US11595045B2

公开(公告)日：2023-02-28

申请号：US17359466

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

IPC: H03K19/1776 ,  H01L25/18 ,  H01L23/367

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

公开(公告)号：US11581235B2

公开(公告)日：2023-02-14

申请号：US17234671

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/34 ,  H01L21/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11031288B2

公开(公告)日：2021-06-08

申请号：US16252420

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Sujit Sharan ,  Ravindranath Mahajan ,  Stefan Rusu ,  Donald S. Gardner

IPC: H01L21/78 ,  H01L23/48 ,  H01L23/522 ,  H01L25/16 ,  H01L49/02 ,  H01L23/538

Abstract: Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

公开(公告)号：US20200273811A1

公开(公告)日：2020-08-27

申请号：US16287665

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mitul Modi ,  Sanka Ganesan ,  Edvin Cetegen ,  Omkar Karhade ,  Ravindranath Mahajan ,  James C. Matayabas, Jr. ,  Jan Krajniak ,  Kumar Singh ,  Aastha Uppal

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/29 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56 ,  H01L23/532

Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US10236209B2

公开(公告)日：2019-03-19

申请号：US14583015

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sujit Sharan ,  Ravindranath Mahajan ,  Stefan Rusu ,  Donald S. Gardner

IPC: H01L21/78 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02 ,  H01L23/538 ,  H01L23/522 ,  H01L27/08

Abstract: Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.