公开(公告)号：US20200160534A1

公开(公告)日：2020-05-21

申请号：US16688403

申请日：2019-11-19

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  John G. Gierach ,  Gabor Liktor ,  Andrew T. Lauritzen

IPC: G06T7/194 ,  H04N19/597 ,  G06T7/11 ,  G06T7/00 ,  G06T15/20 ,  H04N21/00 ,  G06T15/50 ,  H04N21/4402 ,  H04N21/2343 ,  H04N19/436 ,  H04N19/167 ,  H04N21/478 ,  H04N19/132 ,  H04N21/81 ,  H04N19/587 ,  H04N19/46

Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.

公开(公告)号：US20200143579A1

公开(公告)日：2020-05-07

申请号：US16670749

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06T15/00 ,  G06N3/02 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US10522113B2

公开(公告)日：2019-12-31

申请号：US15858486

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G06T15/40 ,  G09G5/36 ,  G09G5/391 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00 ,  G06T3/00 ,  G09G5/397 ,  G06T1/60 ,  G06F3/14 ,  G09G5/377

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US20190205736A1

公开(公告)日：2019-07-04

申请号：US15858014

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Abhishek Venkatesh ,  Gokce Keskin ,  John Gierach ,  Oguz Elibol ,  Tomer Bar-On ,  Huma Abidi ,  Devan Burke ,  Jaikrishnan Menon ,  Eriko Nurvitadhi ,  Pruthvi Gowda Thorehosur Appajigowda ,  Travis T. Schluessler ,  Dhawal Srivastava ,  Nishant Patel ,  Anil Thomas

IPC: G06N3/063 ,  G06N5/04 ,  G06N3/04 ,  G06N99/00 ,  G06F9/38 ,  G06N3/08 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F9/3887 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

公开(公告)号：US20180300903A1

公开(公告)日：2018-10-18

申请号：US15489068

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： John G. Gierach ,  Hugues Labbe ,  Tomer Bar-On ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Philip R. Laws ,  Devan Burke ,  Abhishek R. Appu ,  Peter L. Doyle ,  Elmoustapha Ould-Ahmed-Vall ,  Travis T. Schluessler ,  Altug Koker

IPC: G06T9/00 ,  G06T1/20 ,  G06T7/194 ,  G09G3/00 ,  G06T15/20 ,  G06T15/50 ,  G06T1/60

Abstract: Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data.

公开(公告)号：US20180300145A1

公开(公告)日：2018-10-18

申请号：US15488988

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0811 ,  G06F12/0855 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/455 ,  G06F2212/602 ,  G06F2212/6024 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US20180293777A1

公开(公告)日：2018-10-11

申请号：US15482724

申请日：2017-04-08

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06T15/00 ,  G06N3/04 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240419956A1

公开(公告)日：2024-12-19

申请号：US18749806

申请日：2024-06-21

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsch ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US11886984B2

公开(公告)日：2024-01-30

申请号：US17398302

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06F9/30

CPC classification number: G06N3/063 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30043 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230394305A1

公开(公告)日：2023-12-07

申请号：US18325744

申请日：2023-05-30

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amitai Armon ,  Uzi Sarel

IPC: G06N3/08 ,  G06N20/00 ,  G06N20/10

CPC classification number: G06N3/08 ,  G06N20/10 ,  G06N20/00

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.