公开(公告)号：US20190042403A1

公开(公告)日：2019-02-07

申请号：US15925907

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Yu Du ,  Ryan Norton ,  David J. Pelster ,  Xin Guo

IPC: G06F12/02 ,  G06F7/58

CPC classification number: G06F12/0223 ,  G06F7/58 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/0607 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/7208

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.

公开(公告)号：US09766814B2

公开(公告)日：2017-09-19

申请号：US14822793

申请日：2015-08-10

Applicant: INTEL CORPORATION

Inventor： Xin Guo ,  Feng Zhu ,  Eric L. Hoffman ,  Jing-Jing Li ,  David J. Pelster

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/10 ,  G11C29/00

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/253 ,  G06F2212/657 ,  G11C29/76

Abstract: Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes in the dies extending through the bands define addressable blocks. A first remapping of a logical-to-physical mapping is performed by remapping logical addresses of blocks in a first end of the bands that map to defective physical blocks to map to good physical blocks at a second end of the bands. After performing the first remapping, a second remapping of the logical-to-physical mapping is performed by remapping logical addresses in the second end of bands that map to defective blocks to map to good physical blocks in the first end of bands.

公开(公告)号：US20170090752A1

公开(公告)日：2017-03-30

申请号：US14866192

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Xin Guo ,  David J. Pelster ,  Eric L. Hoffman

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/20 ,  G11C2211/5641

Abstract: An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

公开(公告)号：US09552159B2

公开(公告)日：2017-01-24

申请号：US14877144

申请日：2015-10-07

Applicant: Intel Corporation

Inventor： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0688 ,  G06F11/1417

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Abstract translation: 根据一种配置，存储器系统包括配置管理器和多个存储器设备。 配置管理器包括状态检测逻辑，检索逻辑和配置管理逻辑。 状态检测逻辑接收由第一存储器设备进行的失败尝试的通知，以便通过存储在第一存储器设备中的自定义配置设置进行初始化。 响应于该通知，检索逻辑从存储器系统中的第二存储器设备检索配置设置信息的备份副本。 配置管理逻辑使用从第二存储器设备检索的配置设置信息的备份副本来初始化第一存储器设备。

公开(公告)号：US20160283161A1

公开(公告)日：2016-09-29

申请号：US14672084

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Neal R. Mielke ,  Mark Anthony Golez ,  David J. Pelster ,  Paul D. Ruby ,  Xin Guo

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0652 ,  G06F12/0246

Abstract: Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与用于快速适应输入I / O（输入/输出）工作负载的垃圾收集资源分配的机制相关的方法和装置。 在一个实施例中，非易失性存储器存储对应于第一工作负载和第二工作负载的数据。 至少部分地基于一个或多个块的平均有效性的确定来确定非易失性存储器中的一个或多个资源的分配，其中在第一工作负载的操作期间处理一个或多个候选频带， 第二个工作量。 还公开并要求保护其他实施例。

公开(公告)号：US20160283111A1

公开(公告)日：2016-09-29

申请号：US14670250

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Xin Guo ,  David B. Carlton ,  Scott Nelson ,  David J. Pelster ,  Donia Sebastian

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1626

Abstract: Apparatus, systems, and methods to implement read operations in nonvolatile memory devices are described. In one example, a controller comprises logic to receive a first read request from a host device, place the first read request in a read queue comprising a plurality of read requests directed to the nonvolatile memory, determine a first target die and a first target plane in the nonvolatile memory for the first read request and combine the first read request with at least a second read request in the read queue to form a combined read request, wherein the second read request comprise a second target die, which is the same as the first target die, and a second target plane which is different from the first target plane. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储器件中实现读取操作的装置，系统和方法。 在一个示例中，控制器包括从主机设备接收第一读请求的逻辑，将第一读请求置于包括指向非易失性存储器的多个读请求的读队列中，确定第一目标管芯和第一目标平面 在所述非易失性存储器中用于所述第一读取请求，并将所述第一读取请求与所述读取队列中的至少第二读取请求组合以形成组合的读取请求，其中所述第二读取请求包括第二目标模具，其与 第一目标管芯和与第一靶面不同的第二靶平面。 还公开并要求保护其他实例。

公开(公告)号：US20160155497A1

公开(公告)日：2016-06-02

申请号：US14954002

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

Abstract translation: 电子存储器或控制器可以使用第一类型的读取命令，寻址到电子存储器的存储器的第一页，其包括用于指示电子存储器的第二页存储器尚未被编程的信息和第二类型的读取 命令，寻址到存储器的第一页，其包括用于指示第二页存储器已被编程的信息。 存储器的第一页可以包括多级单元（MLC）的下页，并且第二页存储器可以包括相同MLC的上页。 在使用第一种类型的读取命令的时间段内启用第二页内存。

公开(公告)号：US09236136B2

公开(公告)日：2016-01-12

申请号：US13714763

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G06F12/02 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

Abstract translation: 电子存储器或控制器可以使用第一类型的读取命令，寻址到电子存储器的存储器的第一页，其包括用于指示电子存储器的第二页存储器尚未被编程的信息和第二类型的读取 命令，寻址到存储器的第一页，其包括用于指示第二页存储器已被编程的信息。 存储器的第一页可以包括多级单元（MLC）的下页，并且第二页存储器可以包括相同MLC的上页。 在使用第一种类型的读取命令的时间段内启用第二页内存。

公开(公告)号：US09030885B2

公开(公告)日：2015-05-12

申请号：US14549785

申请日：2014-11-21

Applicant: Intel Corporation

Inventor： Yogesh B Wakchaure ,  Kiran Pangal ,  Xin Guo ,  Qingru Meng ,  Hanmant P Belgal

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C29/028 ,  H01L27/115

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.

公开(公告)号：US20150078088A1

公开(公告)日：2015-03-19

申请号：US14549785

申请日：2014-11-21

Applicant: Intel Corporation

Inventor： Yogesh B Wakchaure ,  Kiran Pangal ,  Xin Guo ,  Qingru Meng ,  Hanmant P Belgal

IPC: G11C16/16

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C29/028 ,  H01L27/115

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.

Abstract translation: 闪存器件可以包括在快闪存储器单元块中被组织为NAND串的两个或更多个闪存单元，以及在相对端耦合到NAND串的闪存单元，用作选择门。 闪速存储器件可以能够向闪存控制器提供与选通门的电压阈值相关的信息，擦除响应于选择栅极擦除命令而用作选择栅极的闪存单元，以及编程用作 响应于选择门程序命令选择门。 闪存控制器可以耦合到闪存设备，并且如果闪存设备提供的信息指示至少一个选择门的电压阈值是 如果由闪速存储器件提供的信息指示至少一个选择门的电压阈值在预定电压范围之外，则将选择门程序命令发送到闪速存储器件。