公开(公告)号：US20190042112A1

公开(公告)日：2019-02-07

申请号：US15927042

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Sarvesh Varakabe Gangadhar ,  Feng Zhu ,  Xin Guo ,  Simon D. Ramage ,  Ning Wu ,  Robert E. Frickey, III

IPC: G06F3/06 ,  G11C16/34 ,  G06F11/30

Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a non-volatile memory, and a processor coupled with the non-volatile memory to perform a scan of a plurality of non-volatile memory dies in a multi-die memory package to detect one or more defective non-volatile memory dies, where an individual non-volatile memory die of the plurality of non-volatile memory dies is defective if the individual non-volatile memory die has a number of bad blocks that exceeds a predefined threshold, and store one or more defective die indicators in a die topology in the non-volatile memory based at least in part on the scan, where the one or more defective die indicators correspond to the one or more defective non-volatile memory dies. Other embodiments may be described and/or claimed.

公开(公告)号：US09535777B2

公开(公告)日：2017-01-03

申请号：US14087282

申请日：2013-11-22

Applicant: Intel Corporation

Inventor： Pranav Kalavade ,  Feng Zhu ,  Shyam Sunder Raghunathan ,  Ravi H. Motwani

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/07 ,  G11B20/18

CPC classification number: G06F11/0751 ,  G06F11/073 ,  G06F11/1012 ,  G11B20/1816

Abstract: Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.

Abstract translation: 管理非易失性存储系统中的缺陷的系统和方法，可用于避免无意中丢失数据，同时尽可能保持非易失性存储系统中有用的内存。 所公开的系统和方法可以监视多个触发事件，用于检测非易失性存储系统中包括的一个或多个非易失性存储器（NVM）设备中的可能缺陷，并且基于类型向相应的NVM设备应用一个或多个缺陷管理策略 的触发事件导致检测到可能的缺陷。 可以主动地使用这种缺陷管理策略来以更小的粒度来在非易失性存储系统中退出内存，将存储器的退出重点集中在可能包含缺陷的非易失性存储器的区域上。

公开(公告)号：US09766814B2

公开(公告)日：2017-09-19

申请号：US14822793

申请日：2015-08-10

Applicant: INTEL CORPORATION

Inventor： Xin Guo ,  Feng Zhu ,  Eric L. Hoffman ,  Jing-Jing Li ,  David J. Pelster

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/10 ,  G11C29/00

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/253 ,  G06F2212/657 ,  G11C29/76

Abstract: Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes in the dies extending through the bands define addressable blocks. A first remapping of a logical-to-physical mapping is performed by remapping logical addresses of blocks in a first end of the bands that map to defective physical blocks to map to good physical blocks at a second end of the bands. After performing the first remapping, a second remapping of the logical-to-physical mapping is performed by remapping logical addresses in the second end of bands that map to defective blocks to map to good physical blocks in the first end of bands.

公开(公告)号：US20170139626A1

公开(公告)日：2017-05-18

申请号：US15419563

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.

公开(公告)号：US09570159B1

公开(公告)日：2017-02-14

申请号：US14884428

申请日：2015-10-15

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G11C11/34 ,  G11C11/56 ,  G11C11/4096 ,  G11C16/22 ,  G11C7/10

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes sending, upon detection of the power loss event, from a processor of the solid state drive, a command to abort an ongoing write operation of an aborted memory cell. In response to an indication that the ongoing write operation is aborted, the data to be written to the aborted memory cell is recovered. A first portion of the data to be written to the aborted memory cell is written to a first memory cell. A second portion of the data to be written to the aborted memory cell is written to a second memory cell.

Abstract translation: 公开了在功率损耗事件期间保存固态驱动器的数据的方法，装置，系统和制品。 一种示例性方法包括在从固态驱动器的处理器检测到功率损耗事件时发送中止正在进行的中止的存储器单元的写入操作的命令。 响应于正在进行的写入操作被中止的指示，将要被写入被中止的存储单元的数据被恢复。 要写入中止的存储单元的数据的第一部分被写入第一存储器单元。 要写入中止的存储单元的数据的第二部分被写入第二存储单元。

公开(公告)号：US09830093B2

公开(公告)日：2017-11-28

申请号：US14672080

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Xin Guo ,  Feng Zhu ,  Yogesh B. Wakchaure ,  David J. Pelster

IPC: G06F3/06 ,  G06F12/10 ,  G06F11/10 ,  G11C11/00 ,  G11C16/26 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/108 ,  G11C11/005 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411

Abstract: Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.

公开(公告)号：US09740419B2

公开(公告)日：2017-08-22

申请号：US15419563

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G11C11/34 ,  G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.

公开(公告)号：US09418000B2

公开(公告)日：2016-08-16

申请号：US14579971

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Shyam Sunder Raghunathan ,  Iwen Chao ,  Xin Guo ,  Pranav Kalavade ,  Krishna K. Parat ,  Feng Zhu

IPC: G11C16/04 ,  G06F12/02 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G06F11/10 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F11/1084 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储器件中实现动态存储器管理的装置，系统和方法。 在一个示例中，控制器包括用于监视非易失性存储器的至少一个性能参数的逻辑，确定何时至少一个性能参数通过指示非易失性存储器性能下降的阈值，以及响应于该至少一个 性能参数通过阈值，以修改非易失性存储器的至少一个操作属性。 还公开并要求保护其他实例。

公开(公告)号：US10437512B2

公开(公告)日：2019-10-08

申请号：US15394261

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Feng Zhu ,  Aliasgar S. Madraswala ,  Xin Guo

IPC: G06F3/06 ,  G11C29/00 ,  G11C7/14 ,  G11C29/52

Abstract: Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

公开(公告)号：US20160283143A1

公开(公告)日：2016-09-29

申请号：US14672080

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Xin Guo ,  Feng Zhu ,  Yogesh B. Wakchaure ,  David J. Pelster

IPC: G06F3/06 ,  G11C14/00 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/108 ,  G11C11/005 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411

Abstract: Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与扁平间接系统中的不同扇形尺寸（VSS）启用的旋转平面XOR方案相关的方法和装置。 在一个实施例中，非易失性存储器将用户数据存储在多个管芯的多个平面的第一组中，并且在第二组多个平面中对应于用户数据的奇偶校验数据。 跨越多个管芯的多个平面的第一组中的用户数据和多个平面中的第二组被旋转以匹配奇偶校验数据的映射。 还公开并要求保护其他实施例。