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    Reduction of forming voltage in semiconductor devices
    41.
    发明申请
    Reduction of forming voltage in semiconductor devices 有权
    降低半导体器件中的形成电压

    公开(公告)号：US20140001431A1

    公开(公告)日：2014-01-02

    申请号：US14018719

    申请日：2013-09-05

    Applicant: Intermolecular Inc.

    Inventor： Pragati KUMAR ,  Tony P. Chiang ,  Prashant B. Phatak ,  Yun Wang

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  G11C13/0002 ,  G11C2013/0083 ,  G11C2213/51 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641

    Abstract: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.

    Abstract translation: 本公开提供了一种非易失性存储器件及相关的制造和操作方法。 该装置可以包括一个或多个电阻随机存取存储器（ReRAM）方法来为存储器装置提供更可预测的操作。 特别地，可以通过使用阻挡层，反极性形成电压脉冲，从下功函电极注入电子的形成电压脉冲或还原环境中的退火来降低特定设计所需的形成电压 。 可以根据期望的应用和结果应用这些技术中的一种或多种。

    Combinatorial process optimization methodology and system
    42.
    发明授权
    Combinatorial process optimization methodology and system 失效
    组合过程优化方法和系统

    公开(公告)号：US08554507B2

    公开(公告)日：2013-10-08

    申请号：US13656939

    申请日：2012-10-22

    Applicant: Intermolecular, Inc.

    Inventor： Prashant B. Phatak

    IPC: G06F19/00

    CPC classification number: G05B19/41865 ,  G05B2219/32015 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

    Abstract: A method for obtaining an optimized process solution from a set of design of experiments in a cost effective manner is provided. An actual experiment is performed and data from the experiments is obtained. Through statistical analysis of the data, coefficients are obtained. These coefficients are input into an experiment simulator where input parameters and conditions are combined with the coefficients to predict an output for the input parameters and conditions. From simulated results, conclusions can be drawn as to sets of input parameters and conditions providing desired results. Thereafter, physical experiments utilizing the input parameters and conditions may be performed to verify the simulated results.

    Abstract translation: 提供了一种以成本有效的方式从一组实验设计中获得优化的处理方案的方法。 执行实际实验并获得实验数据。 通过数据的统计分析，得到系数。 这些系数被输入到实验模拟器中，其中输入参数和条件与系数组合以预测输入参数和条件的输出。 从模拟结果可以得出结论，输入参数和条件的集合提供所需的结果。 此后，可以执行利用输入参数和条件的物理实验来验证模拟结果。

    Bipolar Resistive-Switching Memory with a Single Diode Per Memory Cell
    44.
    发明申请
    Bipolar Resistive-Switching Memory with a Single Diode Per Memory Cell 有权
    具有每个存储单元的单个二极管的双极电阻开关存储器

    公开(公告)号：US20130107607A1

    公开(公告)日：2013-05-02

    申请号：US13720448

    申请日：2012-12-19

    Applicant: INTERMOLECULAR, INC.

    Inventor： Yun Wang ,  Tony P. Chiang ,  Prashant B. Phatak

    IPC: G11C11/36

    CPC classification number: G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

    Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.

    Abstract translation: 根据各种实施例，使用双极开关的电阻式开关存储器元件和存储元件阵列包括仅包括不是齐纳二极管的单个二极管的选择元件。 即使当在二极管的反向偏置方向上施加小于二极管的击穿电压的开关电压时，本文所述的电阻式开关存储元件也可以切换。 存储器元件能够在瞬态脉冲电压对存储元件可见时的非常短的时间内进行切换，因此每个存储器单元可以使用单个二极管。

    Nonvolatile Memory Elements
    45.
    发明申请
    Nonvolatile Memory Elements 有权
    非易失性存储元件

    公开(公告)号：US20130059427A1

    公开(公告)日：2013-03-07

    申请号：US13656585

    申请日：2012-10-19

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Sean Barstow ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B. Phatak ,  Sunil Shanker ,  Wen Wu

    IPC: H01L21/02

    CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

    Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

    Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。

    Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks
    46.
    发明授权
    Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks 有权
    基于缺陷和带工程金属 - 电介质金属叠层的交叉条阵列中的非易失性存储器的当前选择器

    公开(公告)号：US09397141B2

    公开(公告)日：2016-07-19

    申请号：US14294519

    申请日：2014-06-03

    Applicant: Intermolecular, Inc.

    Inventor： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

    IPC: H01L45/00 ,  H01L47/00 ,  H01L27/24 ,  H01L29/872

    CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

    Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

    Doped electrode for DRAM capacitor stack
    47.
    发明授权
    Doped electrode for DRAM capacitor stack 有权
    用于DRAM电容器堆叠的掺杂电极

    公开(公告)号：US09318546B1

    公开(公告)日：2016-04-19

    申请号：US14507418

    申请日：2014-10-06

    Applicant: Intermolecular, Inc.

    Inventor： Prashant B. Phatak

    IPC: H01L21/20 ,  H01L21/28 ,  H01L49/02 ,  H01L27/108 ,  H01L21/02 ,  H01L21/285

    CPC classification number: H01L28/75 ,  H01L21/02197 ,  H01L21/2855 ,  H01L27/108 ,  H01L27/10805 ,  H01L28/65

    Abstract: In some embodiments, a metal oxide second electrode material is formed as part of a MIM DRAM capacitor stack. The second electrode material is doped with one or more dopants. The dopants may influence the crystallinity, resistivity, and/or work function of the second electrode material. The dopants may be uniformly distributed throughout the second electrode material or may be distributed with a gradient in their concentration profile.

    Abstract translation: 在一些实施例中，金属氧化物第二电极材料形成为MIM DRAM电容器堆叠的一部分。 第二电极材料掺杂有一种或多种掺杂剂。 掺杂剂可影响第二电极材料的结晶度，电阻率和/或功函数。 掺杂剂可以均匀分布在整个第二电极材料中，或者可以以它们的浓度分布梯度分布。

    Method to Improve DRAM Performance
    48.
    发明申请
    Method to Improve DRAM Performance 审中-公开
    提高DRAM性能的方法

    公开(公告)号：US20160093625A1

    公开(公告)日：2016-03-31

    申请号：US14502728

    申请日：2014-09-30

    Applicant: Intermolecular, Inc.

    Inventor： Xiangxin Rui ,  Imran Hashim ,  Prashant B. Phatak

    IPC: H01L27/108 ,  H01L49/02

    CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/55

    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. The dielectric layer may include zirconium oxide or doped zirconium oxide. In some embodiments, the conductive metal oxide layer includes niobium oxide.

    Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 电介质层可以包括氧化锆或掺杂氧化锆。 在一些实施例中，导电金属氧化物层包括氧化铌。

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