公开(公告)号：US20210096990A1

公开(公告)日：2021-04-01

申请号：US16588241

申请日：2019-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DEREK E. WILLIAMS ,  GUY L. GUTHRIE ,  HUGH SHEN

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F13/16 ,  G06F9/54 ,  G11C11/409

Abstract: A data processing system includes multiple processing units coupled to a system interconnect including a broadcast address interconnect and a data interconnect. The processing unit includes a processor core that executes memory access instructions and a cache memory, coupled to the processor core, which is configured to store data for access by the processor core. The processing unit is configured to broadcast, on the address interconnect, a cache-inhibited write request and write data for a destination device coupled to the system interconnect. In various embodiments, the initial cache-inhibited request and the write data can be communicated in the same or different requests on the address interconnect.

公开(公告)号：US20190121760A1

公开(公告)日：2019-04-25

申请号：US15792755

申请日：2017-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： RICHARD L. ARNDT ,  FLORIAN AUERNHAMMER ,  WAYNE M. BARRETT ,  ROBERT A. DREHMEL ,  GUY L. GUTHRIE ,  MICHAEL S. SIEGEL ,  WILLIAM J. STARKE

IPC: G06F13/24 ,  G06F13/366 ,  G06F13/40 ,  G06F13/42 ,  G06F9/38

CPC classification number: G06F13/24 ,  G06F9/3836 ,  G06F13/366 ,  G06F13/4068 ,  G06F13/42 ,  G06F2213/2412 ,  G06F2213/2414

Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.

公开(公告)号：US20190042428A1

公开(公告)日：2019-02-07

申请号：US15667330

申请日：2017-08-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GUY L. GUTHRIE ,  MICHAEL S. SIEGEL ,  WILLIAM J. STARKE ,  JEFFREY A. STUECHELI

IPC: G06F12/0831

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/507

Abstract: A technique for operating a data processing system includes transitioning, by a cache, to a highest point of coherency (HPC) for a cache line in a required state without receiving data for one or more segments of the cache line that are needed. The cache issues a command to a lowest point of coherency (LPC) that requests data for the one or more segments of the cache line that were not received and are needed. The cache receives the data for the one or more segments of the cache line from the LPC that were not previously received and were needed.

公开(公告)号：US20190042342A1

公开(公告)日：2019-02-07

申请号：US15667313

申请日：2017-08-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GUY L. GUTHRIE ,  CHARLES MARINO ,  PRAVEEN S. REDDY ,  MICHAEL S. SIEGEL

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F11/0757 ,  G06F11/0784 ,  G06F11/0793

Abstract: A technique for operating a data processing system includes detecting that a processing unit within a first group of processing units in the data processing system has a hang condition. In response to detecting that the processing unit has a hang condition, a command issue rate for the first group of processing units is reduced. One or more other groups of processing units in the data processing system are notified that the first group of processing units has reduced the command issue rate for the first group of processing units. In response to the notifying, respective command issue rates of the other groups of processing units are reduced to reduce a number of commands received by the first group of processing units from the other groups of processing units.

公开(公告)号：US20180350427A1

公开(公告)日：2018-12-06

申请号：US15825418

申请日：2017-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： SANJEEV GHAI ,  GUY L. GUTHRIE ,  HUGH SHEN ,  DEREK E. WILLIAMS

IPC: G11C11/406 ,  G06F9/38 ,  G06F9/54 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3012 ,  G06F12/084 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/0897 ,  G06F2212/601

Abstract: A data processing system includes a plurality of processor cores each having a respective store-through upper level cache and a store-in banked lower level cache. Store requests of the plurality of processor cores destined for the banked lower level cache are buffered in multiple store queues including a first store queue and a second store queue. In response to determining that the multiple store queues contain store requests targeting a common bank of the banked lower level cache, store requests from the first store queue are temporarily favored for selection for issuance to the banked lower level cache over those in the second store queue.

公开(公告)号：US20180349136A1

公开(公告)日：2018-12-06

申请号：US15613231

申请日：2017-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GUY L. GUTHRIE ,  DEREK E. WILLIAMS

IPC: G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/467 ,  G06F12/0813 ,  G06F12/0833 ,  G06F12/0875 ,  G06F2212/452

Abstract: A data processing system implementing a weak memory model includes a plurality of processing units coupled to an interconnect fabric. In response execution of a multicopy atomic store instruction, an initiating processing unit broadcasts a store request on the interconnect fabric to obtain coherence ownership of a target cache line. The initiating processing unit posts a kill request to at least one of the plurality of processing units to request invalidation of a copy of the target cache line. In response to successful posting of the kill request, the initiating processing unit broadcasts a store complete request on the interconnect fabric to enforce completion of the invalidation of the copy of the target cache line. In response to the store complete request receiving a coherence response indicating success, the initiating processing unit permits an update to the target cache line requested by the multicopy atomic store instruction to be atomically visible.

公开(公告)号：US20170293559A1

公开(公告)日：2017-10-12

申请号：US15095577

申请日：2016-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GUY L. GUTHRIE ,  WILLIAM J. STARKE ,  DEREK E. WILLIAMS

IPC: G06F12/08 ,  H04L12/743

CPC classification number: G06F12/0831 ,  G06F12/0893 ,  G06F2212/60 ,  G06F2212/621 ,  H04L45/7457

Abstract: In at least one embodiment, a multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric. In response to a first cache memory snooping on the interconnect fabric a request of an interconnect operation of a second cache memory, the first cache memory allocates a snoop machine to service the request. Responsive to the snoop machine completing its processing of the request and prior to the first cache memory receiving a systemwide coherence response of the interconnect operation, the first cache memory allocates an entry in a data structure to handle completion of processing for the interconnection operation and deallocates the snoop machine. The entry of the data structure protects transfer of coherence ownership of a target cache line from the first cache memory to the second cache memory during a protection window extending at least until the systemwide coherence response is received.

公开(公告)号：US20170293557A1

公开(公告)日：2017-10-12

申请号：US15095642

申请日：2016-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GUY L. GUTHRIE ,  JONATHAN R. JACKSON ,  MICHAEL S. SIEGEL ,  WILLIAM J. STARKE ,  JEFFREY A. STUECHELI ,  DEREK E. WILLIAMS

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/6042 ,  G06F2212/621

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies. A first cache memory in a first vertical cache hierarchy issues on the system interconnect a request for a target cache line. Responsive to the request and prior to receiving a systemwide coherence response for the request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the request. In response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, the first cache memory initiates processing to install the target cache line in the first cache memory.

公开(公告)号：US20170177501A1

公开(公告)日：2017-06-22

申请号：US15083469

申请日：2016-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GUY L. GUTHRIE ,  HUGH SHEN ,  DEREK E. WILLIAMS

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1045 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/524 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/621 ,  G06F2212/682 ,  G06F2212/683

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request. Subsequent memory referent instructions are ordered with respect to the broadcast synchronization request by a synchronization instruction.

公开(公告)号：US20170177421A1

公开(公告)日：2017-06-22

申请号：US14977867

申请日：2015-12-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： GUY L. GUTHRIE ,  HUGH SHEN ,  DEREK E. WILLIAMS

IPC: G06F9/52

CPC classification number: G06F9/524 ,  G06F9/522 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/682 ,  G06F2212/683

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying and synchronization requests of a plurality of concurrently executing hardware threads are received in a shared queue. The plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread, and the synchronization requests includes a synchronization request of the initiating hardware thread. The translation invalidation request is broadcast such that the translation invalidation request is received and processed by the plurality of processor cores to invalidate any translation entry that translates a target address of the translation invalidation request. In response to receiving the synchronization request in the shared queue, the synchronization request is removed from the shared queue, buffered in sidecar logic, iteratively broadcast until all of the plurality of processor cores have completed processing the translation invalidation request, and thereafter removed from the sidecar logic.