公开(公告)号：US10347825B2

公开(公告)日：2019-07-09

申请号：US15436001

申请日：2017-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Joe Lee ,  Christopher J. Penny ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L43/06 ,  H01L43/12 ,  H01L43/08

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

公开(公告)号：US20190013209A1

公开(公告)日：2019-01-10

申请号：US16130596

申请日：2018-09-13

Applicant: International Business Machines Corporation ,  Zeon Corporation

Inventor： Robert L. Bruce ,  Eric A. Joseph ,  Joe Lee ,  Takefumi Suzuki

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

公开(公告)号：US10121676B2

公开(公告)日：2018-11-06

申请号：US15847369

申请日：2017-12-19

Applicant: International Business Machines Corporation ,  Zeon Corporation

Inventor： Robert L. Bruce ,  Eric A. Joseph ,  Joe Lee ,  Takefumi Suzuki

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/311 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

公开(公告)号：US20180240968A1

公开(公告)日：2018-08-23

申请号：US15436001

申请日：2017-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Joe Lee ,  Christopher J. Penny ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

公开(公告)号：US20180122691A1

公开(公告)日：2018-05-03

申请号：US15852151

申请日：2017-12-22

Applicant: International Business Machines Corporation

Inventor： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

公开(公告)号：US09953865B1

公开(公告)日：2018-04-24

申请号：US15335122

申请日：2016-10-26

Applicant: International Business Machines Corporation

Inventor： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238

Abstract: A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.

公开(公告)号：US09905513B1

公开(公告)日：2018-02-27

申请号：US15332194

申请日：2016-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Joe Lee ,  Christopher J. Penny

IPC: H01L29/06 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.

公开(公告)号：US20180040510A1

公开(公告)日：2018-02-08

申请号：US15229470

申请日：2016-08-05

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/7681 ,  H01L21/76834 ,  H01L21/7684 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1021

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

公开(公告)号：US09768113B2

公开(公告)日：2017-09-19

申请号：US15152981

申请日：2016-05-12

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/033 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.