公开(公告)号：US12266607B2

公开(公告)日：2025-04-01

申请号：US17493486

申请日：2021-10-04

Applicant: International Business Machines Corporation

Inventor： Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Kisik Choi ,  Cornelius Brown Peethala ,  Hosadurga Shobha ,  Joe Lee

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

公开(公告)号：US20210151350A1

公开(公告)日：2021-05-20

申请号：US17088136

申请日：2020-11-03

Applicant: Tokyo Electron Limited ,  International Business Machines Corporation

Inventor： Yen-Tien Lu ,  Angelique Raley ,  Joe Lee

IPC: H01L21/768 ,  H01L21/027

Abstract: Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

公开(公告)号：US20210098388A1

公开(公告)日：2021-04-01

申请号：US16586947

申请日：2019-09-28

Applicant: International Business Machines Corporation

Inventor： Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Kisik Choi ,  Cornelius Brown Peethala ,  Hosadurga Shobha ,  Joe Lee

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768

Abstract: Techniques to enable bottom barrier free interconnects without voids. In one aspect, a method of forming interconnects includes: forming metal lines embedded in a dielectric; depositing a sacrificial dielectric over the metal lines; patterning vias and trenches in the sacrificial dielectric down to the metal lines, with the trenches positioned over the vias; lining the vias and trenches with a barrier layer; depositing a conductor into the vias and trenches over the barrier layer to form the interconnects; forming a selective capping layer on the interconnects; removing the sacrificial dielectric in its entirety; and depositing an interlayer dielectric (ILD) to replace the sacrificial dielectric. An interconnect structure is also provided.

公开(公告)号：US10312434B2

公开(公告)日：2019-06-04

申请号：US15805882

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Joe Lee ,  Christopher J. Penny ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

公开(公告)号：US10170416B2

公开(公告)日：2019-01-01

申请号：US15816414

申请日：2017-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Joe Lee ,  Christopher J. Penny

IPC: H01L29/06 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.

公开(公告)号：US20160379929A1

公开(公告)日：2016-12-29

申请号：US15152981

申请日：2016-05-12

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/321 ,  H01L21/033 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract translation: 一种用于在集成电路中形成通孔的方法包括：图案化第一硬掩模中的第一开口，设置在第一有机自平面化聚合物（OPL）层上的第一硬掩模，去除第一OPL层的暴露部分以限定空腔 去除所述空腔中的第二硬掩模的暴露部分，去除设置在所述第二硬掩模下方的第一介电层的暴露部分以进一步限定所述空腔，去除所述空腔中的第一盖层的暴露部分，去除暴露部分 以进一步限定所述空腔，去除第二盖层的暴露部分以进一步限定所述空腔，在所述空腔中的第二导电材料上移除衬里层的暴露部分，以及在所述腔中沉积导电材料 腔。

公开(公告)号：US09373582B1

公开(公告)日：2016-06-21

申请号：US14749140

申请日：2015-06-24

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract translation: 用于在集成电路中形成通孔的方法包括：图案化第一硬掩模中的第一开口，设置在第一有机自平面化聚合物（OPL）层上的第一硬掩模，去除第一OPL层的暴露部分以限定空腔 去除所述空腔中的第二硬掩模的暴露部分，去除设置在所述第二硬掩模下方的第一介电层的暴露部分以进一步限定所述空腔，去除所述空腔中的第一盖层的暴露部分，去除暴露部分 以进一步限定所述空腔，去除第二盖层的暴露部分以进一步限定所述空腔，在所述空腔中的第二导电材料上移除衬里层的暴露部分，以及在所述腔中沉积导电材料 腔。

公开(公告)号：US20160172231A1

公开(公告)日：2016-06-16

申请号：US14567567

申请日：2014-12-11

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Joe Lee ,  Yann Mignot ,  Brown C. Peethala

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76843

Abstract: A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect dielectric material containing a plurality of first conductive metal structures utilizing a titanium nitride hard mask portion located over a second region of the interconnect dielectric material as an etch mask. The titanium nitride hard mask portion located over the second region of the interconnect dielectric material is thereafter removed, again prior to air gap opening formation, utilizing another wet etch process. The wet etching processes are used instead of reactive ion etching.

Abstract translation: 在气隙开口形成之前，使用选择性湿蚀刻工艺，以从包含多个第一导电金属结构的互连电介质材料的第一区域上方除去牺牲氮化物层，所述第一导电金属结构利用位于第二层上的氮化钛硬掩模部分 互连电介质材料的区域作为蚀刻掩模。 此后，在气隙开口形成之前，再次移除位于互连电介质材料的第二区域之上的氮化钛硬掩模部分，利用另一湿蚀刻工艺。 使用湿蚀刻工艺代替反应离子蚀刻。

公开(公告)号：US10713057B2

公开(公告)日：2020-07-14

申请号：US16110178

申请日：2018-08-23

Applicant: International Business Machines Corporation

Inventor： Kenneth L. Ward ,  Dung Q. Nguyen ,  Susan E. Eisen ,  Christopher M. Mueller ,  Joe Lee ,  Deepak K. Singh

IPC: G06F9/30 ,  G06F9/38

Abstract: Method and apparatus for stopping completions using stop codes in an instruction completion table are provided by during a first clock cycle, in response to determining that a given entry in an Instruction Completion Table (ICT) is finalized and is associated with a stop code, completing, according to a program order, instructions included in one or more finalized entries of the ICT located in the ICT before the given entry; during a second clock cycle, after completing the instructions, performing exception processing for a special instruction included in the given entry; and during a third clock cycle, after processing the special instruction, completing, according to the program order, additional instructions in one or more finalized entries located in the ICT after the given entry.

公开(公告)号：US10211138B2

公开(公告)日：2019-02-19

申请号：US15983672

申请日：2018-05-18

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/532 ,  H01L23/528

Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.