公开(公告)号：US10366940B2

公开(公告)日：2019-07-30

申请号：US15835749

申请日：2017-12-08

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L29/49 ,  H01L21/768 ,  H01L23/482 ,  H01L23/485 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US10170416B2

公开(公告)日：2019-01-01

申请号：US15816414

申请日：2017-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Joe Lee ,  Christopher J. Penny

IPC: H01L29/06 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.

公开(公告)号：US20180090588A1

公开(公告)日：2018-03-29

申请号：US15683322

申请日：2017-08-22

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/423 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L23/4821 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US20180090587A1

公开(公告)日：2018-03-29

申请号：US15683316

申请日：2017-08-22

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/423 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L23/4821 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US20140203453A1

公开(公告)日：2014-07-24

申请号：US14222931

申请日：2014-03-24

Applicant: International Business Machines Corporation

Inventor： David V. Horak ,  Elbert Huang ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/522 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

Abstract translation: 公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。 该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件 离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。

公开(公告)号：US10256171B2

公开(公告)日：2019-04-09

申请号：US15683324

申请日：2017-08-22

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L23/482 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US10229851B2

公开(公告)日：2019-03-12

申请号：US15251797

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Takeshi Nogami ,  Christopher J. Penny

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/3115 ,  H01L23/532 ,  H01L23/522

Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

公开(公告)号：US09905513B1

公开(公告)日：2018-02-27

申请号：US15332194

申请日：2016-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Joe Lee ,  Christopher J. Penny

IPC: H01L29/06 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.

公开(公告)号：US08828862B2

公开(公告)日：2014-09-09

申请号：US14222931

申请日：2014-03-24

Applicant: International Business Machines Corporation

Inventor： David V. Horak ,  Elbert Huang ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/522 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

公开(公告)号：US10242933B2

公开(公告)日：2019-03-26

申请号：US15683316

申请日：2017-08-22

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L23/482 ,  H01L29/78 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/768

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.