公开(公告)号：US09202900B2

公开(公告)日：2015-12-01

申请号：US14500021

申请日：2014-09-29

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  Kevin K. Chan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/10 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/732 ,  H01L21/8228

CPC classification number: H01L29/7371 ,  H01L21/82285 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

Abstract translation: 一种形成异质结双极晶体管的方法。 该方法包括提供包括至少本征基极区域和发射极基座区域的结构。 在本征基区上形成堆叠。 堆叠包括多晶硅层和顶部牺牲氧化物层。 在结构中形成沟槽。 沟槽围绕内在的基极区域和叠层。 在堆叠周围的两个区域形成一个非本征基。 外部基极通过选择性外延生长工艺形成，以在沟槽上形成桥。 桥梁连接两个地区。 在堆栈中提供一个开口。 开口暴露了内在基础区域的一部分。 在开口中形成发射体。

公开(公告)号：US09105677B2

公开(公告)日：2015-08-11

申请号：US14059531

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu ,  James S. Nakos

IPC: H01L29/732 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66242 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

Abstract translation: 根据本文中具有晶体管顶部和晶体管底部的双极晶体管结构，位于晶体管底部的硅衬底具有第一导电类型的集电极区域。 相对于晶体管顶部和底部，第二导电类型的外延基底层覆盖集电极区域的一部分。 外延基底层在硅衬底上具有底表面和与底表面相对的顶表面。 外延基底层相对于晶体管顶部和底部的顶部区域包含具有足以避免影响晶体管参数并且足以抵抗选择性化学蚀刻的原子组成的锗浓度。 第一导电类型的硅发射极层相对于晶体管顶部和底部覆盖与外延基底层的顶表面相邻的外延基底层的一部分。

公开(公告)号：US09093491B2

公开(公告)日：2015-07-28

申请号：US13705717

申请日：2012-12-05

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James R. Elliott ,  David L. Harame ,  Marwan H. Khater ,  Robert K. Leidy ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L21/8222 ,  H01L29/73 ,  H01L29/737 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0649 ,  H01L29/045 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66257 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7325 ,  H01L29/7375

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 器件结构包括集电极区域，形成在集电极区域上的本征基极，与本征基极耦合并与集电极与本征基极分离的发射极，以及延伸穿过本征基极到集电极区域的隔离区域。 隔离区形成有具有延伸穿过本征基底的第一侧壁的第一部分和具有延伸到收集器区域中的第二侧壁的第二部分。 第二侧壁相对于第一侧壁倾斜。 隔离区域位于形成有第一和第二蚀刻工艺的沟槽中，其中后者以不同的蚀刻速率蚀刻单晶半导体材料的不同晶体方向。

公开(公告)号：US09093478B1

公开(公告)日：2015-07-28

申请号：US14250725

申请日：2014-04-11

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Qizhi Liu ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L21/36 ,  H01L29/66 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10826 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. A method of forming an IC structure according to the present disclosure can include: forming a layered dummy structure on a bulk substrate, wherein the layered dummy structure includes: a first crystalline semiconductive layer; a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the second crystalline semiconductive layer comprises a material distinct from the first crystalline semiconductive layer; and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the same material as the first crystalline semiconductive layer; forming a semiconductor fin on the layered dummy structure, wherein the semiconductor fin comprises part of a finFET structure; and selectively removing the layered dummy structure to form a cavity between the bulk substrate and the semiconductor fin.

Abstract translation: 本公开通常提供具有体硅片finFET的集成电路（IC）结构及其形成方法。 根据本公开的形成IC结构的方法可以包括：在体基板上形成分层虚拟结构，其中所述分层虚拟结构包括：第一晶体半导体层; 位于所述第一晶体半导体层上的第二晶体半导体层，其中所述第二晶体半导体层包括与所述第一晶体半导体层不同的材料; 以及位于所述第二晶体半导体层上的第三晶体半导体层，其中所述第三晶体半导体层包含与所述第一晶体半导体层相同的材料; 在所述分层虚拟结构上形成半导体鳍片，其中所述半导体鳍片包括finFET结构的一部分; 并且选择性地去除分层虚拟结构以在体基板和半导体鳍之间形成空腔。

公开(公告)号：US20150206959A1

公开(公告)日：2015-07-23

申请号：US14673958

申请日：2015-03-31

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/165 ,  H01L29/06 ,  H01L29/732

CPC classification number: H01L29/7371 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/465 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.

Abstract translation: 公开了沟槽形成技术，其中第一蚀刻工艺形成通过半导体层进入半导体衬底的开口，然后第二蚀刻工艺扩展衬底内部的开口部分以形成沟槽。 然而，在第二蚀刻之前，在开口的底表面处的衬底中形成掺杂区域。 然后，进行第二蚀刻，使得在开口侧壁处的衬底的未掺杂区域以比掺杂区更快的蚀刻速率被蚀刻，从而确保沟槽具有相对高的纵横比。 还公开了一种双极半导体器件形成方法。 该方法结合沟槽形成技术，使得围绕集电极基座形成的沟槽隔离区域具有高纵横比，从而使集电极到基极电容Ccb和集电极电阻Rc都最小化。

公开(公告)号：US20150194510A1

公开(公告)日：2015-07-09

申请号：US14151225

申请日：2014-01-09

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Peng Cheng ,  Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/73 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7371

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 在半导体衬底上形成本征基极层，在本征基极层上形成蚀刻停止层，在蚀刻停止层上形成非本征基极层。 形成沟槽，其穿过外部基极层到蚀刻停止层。 通过蚀刻对蚀刻停止层选择性的非本征基层形成沟槽。 通过蚀刻对本征基极层有选择性的蚀刻停止层，第一沟槽通过蚀刻停止层延伸到本征基极层。 在沟槽延伸通过蚀刻停止层之后，使用沟槽形成发射极。

公开(公告)号：US09059233B2

公开(公告)日：2015-06-16

申请号：US14083774

申请日：2013-11-19

Applicant: International Business Machines Corporation

Inventor： Robert K. Leidy ,  Mark D. Levy ,  Qizhi Liu ,  Gary L. Milo

IPC: H01L29/66 ,  H01L29/73 ,  H01L29/737 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L29/737 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance Ccb and collector resistance Rc are minimized within the resulting bipolar semiconductor device.

Abstract translation: 公开了一种沟槽形成技术，其中具有具有平面轮廓的第一侧壁和具有锯齿轮廓的第二侧壁的开口被蚀刻通过半导体层并进入半导体衬底。 然后，晶体湿法蚀刻工艺使半导体衬底内的开口的部分膨胀以形成沟槽。 由于侧壁的轮廓不同，因此不同的晶体取向，一个侧壁比另一个侧壁更快地蚀刻，导致不对称的沟槽。 还公开了一种双极半导体器件形成方法，其在形成沟槽绝缘区域时结合上述沟槽形成技术，该沟槽隔离区域切割外部基极区域并且围绕收集器基座。 沟槽的不对称性确保沟槽隔离区域具有相对较窄的宽度，从而确保集电极到基极电容Ccb和集电极电阻Rc在所得双极半导体器件内最小化。

公开(公告)号：US20150108548A1

公开(公告)日：2015-04-23

申请号：US14059531

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu ,  James S. Nakos

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66242 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

Abstract translation: 根据本文中具有晶体管顶部和晶体管底部的双极晶体管结构，位于晶体管底部的硅衬底具有第一导电类型的集电极区域。 相对于晶体管顶部和底部，第二导电类型的外延基底层覆盖集电极区域的一部分。 外延基底层在硅衬底上具有底表面和与底表面相对的顶表面。 外延基底层相对于晶体管顶部和底部的顶部区域包含具有足以避免影响晶体管参数并且足以抵抗选择性化学蚀刻的原子组成的锗浓度。 第一导电类型的硅发射极层相对于晶体管顶部和底部覆盖与外延基底层的顶表面相邻的外延基底层的一部分。

公开(公告)号：US20150091129A1

公开(公告)日：2015-04-02

申请号：US14041716

申请日：2013-09-30

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Qizhi Liu ,  Zhenzhen Ye ,  Yan Zhang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/7624 ,  H01L21/76283

Abstract: An isolation structure can include a structure material with thermal conductivity greater than silicon dioxide, yet electrical conductivity such that the structure material can replace silicon dioxide as an insulator. At least one column can extend to a target layer from a top surface of a semiconductor device near an active area of the device. At least one lateral portion can extend from the column(s) substantially parallel to the target layer and can extend between multiple columns in the target layer, such as in a cavity formed by lateral etching. The structure material can include, for example, aluminum nitride (AlN).

Abstract translation: 隔离结构可以包括导热率大于二氧化硅的结构材料，但是导电性使得结构材料可以代替二氧化硅作为绝缘体。 至少一列可以从设备的有效区域附近的半导体器件的顶表面延伸到目标层。 至少一个横向部分可以从基本上平行于目标层的柱延伸并且可以在目标层中的多个柱之间延伸，例如在通过横向蚀刻形成的空腔中。 结构材料可以包括例如氮化铝（AlN）。

公开(公告)号：US20150014747A1

公开(公告)日：2015-01-15

申请号：US14500021

申请日：2014-09-29

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  Kevin K. Chan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7371 ,  H01L21/82285 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

Abstract translation: 一种形成异质结双极晶体管的方法。 该方法包括提供包括至少本征基极区域和发射极基座区域的结构。 在本征基区上形成堆叠。 堆叠包括多晶硅层和顶部牺牲氧化物层。 在结构中形成沟槽。 沟槽围绕内在的基极区域和叠层。 在堆叠周围的两个区域形成一个非本征基。 外部基极通过选择性外延生长工艺形成，以在沟槽上形成桥。 桥梁连接两个地区。 在堆栈中提供一个开口。 开口暴露了内在基础区域的一部分。 在开口中形成发射体。