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公开(公告)号:US20210158866A1
公开(公告)日:2021-05-27
申请号:US16692263
申请日:2019-11-22
Applicant: International Business Machines Corporation
Inventor: Saravanan Sethuraman , Karthick Rajamani , Venkata K. Tavva , Hillery Hunter , Chitra Subramanian
IPC: G11C11/56 , G11C11/406
Abstract: A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.
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公开(公告)号:US10740177B2
公开(公告)日:2020-08-11
申请号:US15872097
申请日:2018-01-16
Applicant: International Business Machines Corporation
Inventor: Saravanan Sethuraman , Diyanesh B. Chinnakkonda Vidyapoornachary , Sridhar Rangarajan , Kirk D. Peterson , John B. Deforge
Abstract: Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.
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公开(公告)号:US20200075079A1
公开(公告)日:2020-03-05
申请号:US16674235
申请日:2019-11-05
Applicant: International Business Machines Corporation
Inventor: Kyu-hyoun Kim , Warren E. Maule , Kevin M. Mcilvain , Saravanan Sethuraman
IPC: G11C11/4076 , G11C11/24 , G11C11/4093 , G11C29/00 , G11C16/04 , G11C29/04 , G11C5/04
Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.
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公开(公告)号:US10452470B2
公开(公告)日:2019-10-22
申请号:US15969803
申请日:2018-05-03
Applicant: International Business Machines Corporation
IPC: G06F11/14 , G06F11/07 , G11C11/4096 , G06F11/16
Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.
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公开(公告)号:US10223004B2
公开(公告)日:2019-03-05
申请号:US15093372
申请日:2016-04-07
Applicant: International Business Machines Corporation
Inventor: Saravanan Sethuraman , Gary A. Tressler , Harish Venkataraman
IPC: G06F3/06
Abstract: Embodiments herein describe a 3D flash memory system that includes multiple blocks where each block contains multiple pages arranged in a vertical stack. Instead of having a single command line indicating whether a read or program is to be performed, separate command lines are coupled to each of the blocks. As a result, if the memory system identifies a read request and a program request to different blocks, the requests can be performed in parallel. In one embodiment, a program command line is used to perform a program request on a first block while a read command line is used to perform a read request on a second block in the 3D flash memory system in parallel. Furthermore, because a program request can take much longer to complete than a read request, the 3D flash memory system can perform multiple read requests in parallel with the program request.
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公开(公告)号:US10218713B2
公开(公告)日:2019-02-26
申请号:US16025124
申请日:2018-07-02
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Abstract: A method, computer program product, and system for authenticating a computing device by geographic attestation includes a processor utilizing executing an authentication application utilizing location services executing on the computing device to obtain location data from the location services. The processor obtains the location data and creates and encodes a data structure in a secured area of a memory; the data structure is only accessible to the authentication application. The processor transmits to an authentication server, an authentication request that includes the encoded location data, requesting access to secure content. The processor obtains a request to query identifiers proximate to the computing device for additional location information and queries the identifiers and transmits this additional location information to the authentication server. The processor receives a notification and based on obtaining the notification, erases the secured area and turns off the location services on the computing device.
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公开(公告)号:US10078587B2
公开(公告)日:2018-09-18
申请号:US14680153
申请日:2015-04-07
Applicant: International Business Machines Corporation
Inventor: Timothy J. Dell , Shwetha Janardhan , Sairam Kamaraju , Saravanan Sethuraman
IPC: G06F12/00 , G06F12/0806 , G06F12/0811 , G06F12/0817 , G06F12/0897
CPC classification number: G06F12/0806 , G06F12/0811 , G06F12/0822 , G06F12/0897 , G06F2212/1032 , G06F2212/283 , G06F2212/313 , G06F2212/621
Abstract: In one aspect a method includes determining, by a controller of a memory system, that a cache line of one of a plurality of levels of cache in the memory system has been modified. An aspect also includes copying the modified cache line to an auxiliary storage element, and setting a flag in a cache directory for the modified cache line to indicate a cache state of mirrored modified.
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公开(公告)号:US09915987B2
公开(公告)日:2018-03-13
申请号:US14611480
申请日:2015-02-02
Applicant: International Business Machines Corporation
CPC classification number: G06F1/206 , G05D23/1928 , G05D23/1932 , H05K7/20145 , H05K7/20727
Abstract: A method, system and computer program product for implementing thermal air flow control management of a computer system. A temperature profile of the server system is identified. One or more dual in-line memory-modules (DIMMs) are used to pivot on an axis to direct air flow to cool identified hot spots based upon the temperature profile of the server system.
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公开(公告)号:US09875036B2
公开(公告)日:2018-01-23
申请号:US15404232
申请日:2017-01-12
Applicant: International Business Machines Corporation
Inventor: Diyanesh B. Chinnakkonda Vidyapoornachary , Kyu-hyoun Kim , Saravanan Sethuraman , Gary A. Tressler
CPC classification number: G06F3/0616 , G06F3/061 , G06F3/0619 , G06F3/0655 , G06F3/0679 , G06F3/0688 , G06F11/0727 , G06F11/076 , G06F11/0793 , G11C5/04 , G11C5/141 , G11C16/349 , G11C16/3495
Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
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公开(公告)号:US20170160956A1
公开(公告)日:2017-06-08
申请号:US14957180
申请日:2015-12-02
Applicant: International Business Machines Corporation
Inventor: Diyanesh B. Chinnakkonda Vidyapoornachary , Kyu-hyoun Kim , Saravanan Sethuraman , Gary A. Tressler
CPC classification number: G06F3/0616 , G06F3/061 , G06F3/0619 , G06F3/0655 , G06F3/0679 , G06F3/0688 , G06F11/0727 , G06F11/076 , G06F11/0793 , G11C5/04 , G11C5/141 , G11C16/349 , G11C16/3495
Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
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