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    Semiconductor Device Comprising a Transistor Including a Body Contact Portion and Method for Manufacturing the Semiconductor Device
    41.
    发明申请
    Semiconductor Device Comprising a Transistor Including a Body Contact Portion and Method for Manufacturing the Semiconductor Device 审中-公开
    包括体接触部分的晶体管的半导体器件和用于制造半导体器件的方法

    公开(公告)号：US20160307891A1

    公开(公告)日：2016-10-20

    申请号：US15096629

    申请日：2016-04-12

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Till Schloesser

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

    CPC classification number: H01L29/4175 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

    Abstract: A semiconductor device comprises a transistor in a semiconductor body having a main surface. The transistor comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the main surface. The gate electrode is disposed in a trench extending in the first direction. The semiconductor device further comprises a source contact electrically connected to the source region and to a source terminal. The source contact is disposed in a source contact opening in the main surface. The semiconductor device further comprises a body contact portion electrically connected to the source terminal and to the body region. The body contact portion vertically overlaps with the source region.

    Abstract translation: 半导体器件包括具有主表面的半导体本体中的晶体管。 晶体管包括源区域，漏极区域，体区域，漂移区域和在身体区域处的栅电极。 主体区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于主表面。 栅电极设置在沿第一方向延伸的沟槽中。 半导体器件还包括电源连接到源极区域和源极端子的源极触点。 源触点设置在主表面中的源极接触开口中。 半导体器件还包括电连接到源极端子和主体区域的主体接触部分。 身体接触部垂直与源区重叠。

    Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device
    42.
    发明申请
    Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device 有权
    半导体器件，集成电路和制造半导体器件的方法

    公开(公告)号：US20160268423A1

    公开(公告)日：2016-09-15

    申请号：US14656041

    申请日：2015-03-12

    Applicant: Infineon Technologies AG

    Inventor： Karoline Koepp ,  Andreas Meiser ,  Till Schloesser

    IPC: H01L29/78 ,  H01L29/40 ,  H01L27/088

    CPC classification number: H01L29/7825 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66681 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7835

    Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The gate electrode is disposed in trenches extending in a first direction parallel to the first main surface. The gate electrode is electrically coupled to a gate terminal. The channel region and the drift zone are disposed along the first direction between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. The conductive layer is electrically connected to the gate terminal.

    Abstract translation: 半导体器件包括具有第一主表面的半导体衬底中的晶体管。 晶体管包括源极区域，漏极区域，沟道区域，漂移区域和与沟道区域的至少两侧相邻的栅电极。 栅电极设置在与第一主表面平行的第一方向上延伸的沟槽中。 栅极电连接到栅极端子。 沟道区域和漂移区沿着源极区域和漏极区域之间的第一方向设置。 半导体器件还包括在栅电极下方并与栅电极绝缘的导电层。 导电层电连接到栅极端子。

    Method of Manufacturing a Semiconductor Device and Semiconductor Device
    45.
    发明申请
    Method of Manufacturing a Semiconductor Device and Semiconductor Device 有权
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20160093731A1

    公开(公告)日：2016-03-31

    申请号：US14868909

    申请日：2015-09-29

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Till Schloesser

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/265 ,  H01L29/40 ,  H01L29/10

    CPC classification number: H01L29/7825 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7835

    Abstract: A method of manufacturing a semiconductor device including a transistor comprises forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches, forming a field dielectric layer in the field plate trenches, thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches, and forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches. The method further comprising forming a source region and forming a drain region in the main surface of the semiconductor substrate.

    Abstract translation: 制造包括晶体管的半导体器件的方法包括在半导体衬底的主表面中形成场板沟槽，在相邻的场板沟槽之间限定漂移区，在场板栅沟中形成场介电层，之后形成栅极 在半导体衬底的主表面中的沟槽，沟道区域被限定在相邻栅极沟槽之间，并且在至少一些场板沟槽和至少一些栅极沟槽中形成导电材料。 该方法还包括形成源极区域并在半导体衬底的主表面中形成漏极区域。

    Integrated circuit and method of manufacturing an integrated circuit
    47.
    发明授权
    Integrated circuit and method of manufacturing an integrated circuit 有权
    集成电路和集成电路制造方法

    公开(公告)号：US09129820B2

    公开(公告)日：2015-09-08

    申请号：US13951099

    申请日：2013-07-25

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

    IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02

    CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

    Abstract: An integrated circuit is formed in a semiconductor substrate. The integrated circuit includes a trench formed in a first main surface of the semiconductor substrate. The trench includes a first trench portion and a second trench portion. The first trench portion is connected with the second trench portion. Openings of the first and second trench portions are adjacent to the first main surface. The integrated circuit further includes a trench transistor structure including a gate electrode disposed in the first trench portion, and a trench capacitor structure including a capacitor dielectric and a first capacitor electrode. The capacitor dielectric and the first capacitor electrode are disposed in the second trench portion. The first capacitor electrode includes a layer conformal with a sidewall of the second trench portion.

    Abstract translation: 在半导体衬底中形成集成电路。 集成电路包括形成在半导体衬底的第一主表面中的沟槽。 沟槽包括第一沟槽部分和第二沟槽部分。 第一沟槽部分与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分的开口与第一主表面相邻。 集成电路还包括沟槽晶体管结构，其包括设置在第一沟槽部分中的栅电极和包括电容器电介质和第一电容器电极的沟槽电容器结构。 电容器电介质和第一电容器电极设置在第二沟槽部分中。 第一电容器电极包括与第二沟槽部分的侧壁共形的层。

    Semiconductor Device and Method for Producing a Semiconductor Device
    49.
    发明申请
    Semiconductor Device and Method for Producing a Semiconductor Device 有权
    用于制造半导体器件的半导体器件和方法

    公开(公告)号：US20150137226A1

    公开(公告)日：2015-05-21

    申请号：US14548375

    申请日：2014-11-20

    Applicant: Infineon Technologies AG

    Inventor： Till Schloesser ,  Andreas Meiser

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734

    Abstract: A semiconductor device includes a semiconductor substrate having first regions of a first conductivity type and body regions of the first conductivity type, which are arranged in a manner adjoining the first region and overlap the latter in each case on a side of the first region which faces a first surface of the semiconductor substrate, and having a multiplicity of drift zone regions arranged between the first regions and composed of a semiconductor material of a second conductivity type, which is different than the first conductivity type. The first regions and the drift zone regions are arranged alternately and form a superjunction structure. The semiconductor device further includes a gate electrode formed in a trench in the semiconductor substrate.

    Abstract translation: 半导体器件包括具有第一导电类型的第一区域和第一导电类型的主体区域的半导体衬底，它们以与第一区域相邻的方式布置，并且在每种情况下与第一区域的第一区域重叠， 半导体衬底的第一表面，并且具有布置在第一区域之间并由与第一导电类型不同的第二导电类型的半导体材料构成的多个漂移区域。 第一区域和漂移区域交替布置并形成超结构结构。 半导体器件还包括形成在半导体衬底中的沟槽中的栅电极。

    Integrated Circuit and Method of Manufacturing an Integrated Circuit
    50.
    发明申请
    Integrated Circuit and Method of Manufacturing an Integrated Circuit 有权
    集成电路和集成电路制造方法

    公开(公告)号：US20150028408A1

    公开(公告)日：2015-01-29

    申请号：US13951099

    申请日：2013-07-25

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

    IPC: H01L27/06 ,  H01L49/02

    CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

    Abstract: An integrated circuit is formed in a semiconductor substrate. The integrated circuit includes a trench formed in a first main surface of the semiconductor substrate. The trench includes a first trench portion and a second trench portion. The first trench portion is connected with the second trench portion. Openings of the first and second trench portions are adjacent to the first main surface. The integrated circuit further includes a trench transistor structure including a gate electrode disposed in the first trench portion, and a trench capacitor structure including a capacitor dielectric and a first capacitor electrode. The capacitor dielectric and the first capacitor electrode are disposed in the second trench portion. The first capacitor electrode includes a layer conformal with a sidewall of the second trench portion.

    Abstract translation: 在半导体衬底中形成集成电路。 集成电路包括形成在半导体衬底的第一主表面中的沟槽。 沟槽包括第一沟槽部分和第二沟槽部分。 第一沟槽部分与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分的开口与第一主表面相邻。 集成电路还包括沟槽晶体管结构，其包括设置在第一沟槽部分中的栅电极和包括电容器电介质和第一电容器电极的沟槽电容器结构。 电容器电介质和第一电容器电极设置在第二沟槽部分中。 第一电容器电极包括与第二沟槽部分的侧壁共形的层。

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