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    Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
    41.
    发明申请
    Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints 审中-公开
    用于提高根端口和根端口集成端点恢复时间的方法，设备和系统

    公开(公告)号：US20160209912A1

    公开(公告)日：2016-07-21

    申请号：US14757924

    申请日：2015-12-24

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Robert E. Gough

    IPC: G06F1/32

    CPC classification number: G06F1/3243 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/325 ,  G06F9/4418 ,  G06F13/42 ,  H04L49/15 ,  Y02D10/151 ,  Y02D50/20

    Abstract: A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.

    Abstract translation: 一种串行点对点链路接口，用于实现处理器和设备之间的通信，高速串行点对点链路接口包括传输串行数据的发送器，接收器反序列化串行数据，以及控制逻辑来实现 一个协议栈。 协议栈支持多个功率管理状态，包括其中维持供电电压的有效状态，第一关闭状态和不向设备提供电源电压的第二关闭状态。 协议栈提供默认恢复时间，以允许设备在访问设备之前开始从第一个关闭状态到活动状态的转换。 协议栈进一步提供在默认恢复时间到期之前访问设备，以完成基于设备通告的恢复时间的转换。

    Optimized link training and management mechanism
    43.
    发明授权
    Optimized link training and management mechanism 有权
    优化链接培训与管理机制

    公开(公告)号：US09141577B2

    公开(公告)日：2015-09-22

    申请号：US14109061

    申请日：2013-12-17

    Applicant: INTEL CORPORATION

    Inventor： Mahesh Wagh ,  David J. Harriman

    IPC: H04L12/50 ,  H04L12/66 ,  H04Q11/00 ,  G06F13/42 ,  G06F13/38 ,  G06F1/32

    CPC classification number: G06F13/4282 ,  G06F1/3253 ,  G06F13/385 ,  H04Q2213/13003 ,  Y02D10/151 ,  Y02D50/20

    Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，可以使用融合协议栈来将通信从第一通信协议统一到第二通信协议，以提供跨物理互连的数据传输。 该堆叠可以并入包括用于包括交易和链路层的第一通信协议的协议栈的装置，以及耦合到协议栈的物理（PHY）单元，以在设备和耦合到装置的设备之间通信 一个物理链接。 该PHY单元可以包括根据第二通信协议的物理单元电路。 描述和要求保护其他实施例。

    Power management for a system on a chip (SoC)
    44.
    发明授权
    Power management for a system on a chip (SoC) 有权
    芯片系统的电源管理（SoC）

    公开(公告)号：US08850247B2

    公开(公告)日：2014-09-30

    申请号：US13925999

    申请日：2013-06-25

    Applicant: Intel Corporation

    Inventor： Woojong Han ,  Madhu Athreya ,  Ken Shoemaker ,  Arvind Mandhani ,  Mahesh Wagh ,  Ticky Thakkar

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

    Abstract: In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法 在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。 描述和要求保护其他实施例。

    Optimized Link Training And Management Mechanism
    45.
    发明申请
    Optimized Link Training And Management Mechanism 有权
    优化链接培训与管理机制

    公开(公告)号：US20130318264A1

    公开(公告)日：2013-11-28

    申请号：US13859042

    申请日：2013-04-09

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  David J. Harriman

    IPC: G06F13/38

    CPC classification number: G06F13/4282 ,  G06F1/3253 ,  G06F13/385 ,  H04Q2213/13003 ,  Y02D10/151 ,  Y02D50/20

    Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，可以使用融合协议栈来将通信从第一通信协议统一到第二通信协议以提供跨物理互连的数据传输。 该堆叠可以并入包括用于包括交易和链路层的第一通信协议的协议栈的装置，以及耦合到协议栈的物理（PHY）单元，以在设备和耦合到装置的设备之间通信 一个物理链接。 该PHY单元可以包括根据第二通信协议的物理单元电路。 描述和要求保护其他实施例。

    LINK LAYER-PHY INTERFACE ADAPTER
    46.
    发明申请
    LINK LAYER-PHY INTERFACE ADAPTER 有权

    公开(公告)号：US20250013600A1

    公开(公告)日：2025-01-09

    申请号：US18648122

    申请日：2024-04-26

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Swadesh Choudhary ,  Mahesh Wagh ,  Lakshmipriya Seshan

    IPC: G06F13/42 ,  G06F13/28

    Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

    TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM INTERCONNECTS
    47.
    发明申请
    TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM INTERCONNECTS 有权

    公开(公告)号：US20210399982A1

    公开(公告)日：2021-12-23

    申请号：US17391557

    申请日：2021-08-02

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

    IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931

    Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

    Multichip package link error detection
    48.
    发明授权
    Multichip package link error detection 有权

    公开(公告)号：US11061761B2

    公开(公告)日：2021-07-13

    申请号：US16779391

    申请日：2020-01-31

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

    IPC: G06F11/10 ,  H03M13/00 ,  H04L29/06 ,  H04L1/00 ,  H04L1/20 ,  G06F13/16 ,  H04L1/16

    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

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