公开(公告)号：US20230420368A1

公开(公告)日：2023-12-28

申请号：US17851985

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/66439 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775

Abstract: Structures having memory with backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. One of the metal layers includes an array of uninterrupted signal lines. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a ground metal line.

公开(公告)号：US20230317145A1

公开(公告)日：2023-10-05

申请号：US17711286

申请日：2022-04-01

Applicant: INTEL CORPORATION

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Wilfred GOMES ,  Rajabali KODURI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094

Abstract: Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. In one embodiment, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, both first and second arrays to store data of a processor, the second plurality of memory cells implementing a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

公开(公告)号：US20230315331A1

公开(公告)日：2023-10-05

申请号：US17711394

申请日：2022-04-01

Applicant: INTEL CORPORATION

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Rajabali KODURI

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

公开(公告)号：US20230005526A1

公开(公告)日：2023-01-05

申请号：US17943044

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: G11C11/406 ,  H01L25/065 ,  H01L25/18

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.

公开(公告)号：US20220271022A1

公开(公告)日：2022-08-25

申请号：US17742205

申请日：2022-05-11

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Glenn J. HINTON ,  Rajesh KUMAR

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

公开(公告)号：US20220139896A1

公开(公告)日：2022-05-05

申请号：US17574485

申请日：2022-01-12

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark T. BOHR ,  Rajesh KUMAR ,  Robert L. SANKMAN ,  Ravindranath V. MAHAJAN ,  Wesley D. MC CULLOUGH

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/16 ,  H01L23/522 ,  H01L23/48 ,  H01L23/538 ,  H01L23/498

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US20220102344A1

公开(公告)日：2022-03-31

申请号：US17033509

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/092 ,  H01L29/40 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06 ,  H01L23/538

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220102339A1

公开(公告)日：2022-03-31

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L21/765 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20210375825A1

公开(公告)日：2021-12-02

申请号：US17398831

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark T. BOHR ,  Udi SHEREL ,  Leonard M. NEIBERG ,  Nevine NASSIF ,  Wesley D. MC CULLOUGH

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

公开(公告)号：US20200258759A1

公开(公告)日：2020-08-13

申请号：US16635539

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Ravindranath V. MAHAJAN ,  Ram S. VISWANATH

IPC: H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/367

Abstract: Techniques and mechanisms for conducting heat with a packaged integrated circuit (IC) device. In an embodiment, the IC device comprises a package substrate and one or more IC dies coupled thereto, where a thermal conductor of the IC device extends through the package substrate. A thermal conductivity of the thermal conductor is more than 20 Watts per meter per degree Kelvin (W/mK). In another embodiment, thermal conductor further extends at least partially through a mold compound disposed on the one or more IC dies.