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41.
公开(公告)号:US11894436B2
公开(公告)日:2024-02-06
申请号:US17543028
申请日:2021-12-06
发明人: Julien Frougier , Ruilong Xie , Nicolas Loubet , Andrew M. Greene , Veeraraghavan S. Basker , Balasubramanian S. Pranatharthiharan
IPC分类号: H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号: H01L29/42392 , H01L29/0673 , H01L29/66545 , H01L29/78696
摘要: A CFET (complementary field effect transistor) structure including a substrate, a first CFET formed above the substrate, and a second CFET formed above the substrate. The first CFET includes a top FET and a bottom FET. The top FET and bottom FET of the first CFET include at least one nanosheet channel. A gate affiliated with the first CFET and the second CFET devices includes a continuous horizontal dielectric over the entire length of the gate. The top FET of each CFET has a first polarity. The bottom FET of each a CFET comprises a second polarity. The top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal.
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42.
公开(公告)号:US20230282722A1
公开(公告)日:2023-09-07
申请号:US17653468
申请日:2022-03-04
发明人: Julien Frougier , Sagarika Mukesh , Albert M Chu , Ruilong Xie , Andrew M. Greene , Eric Miller , Junli Wang , Veeraraghavan S. Basker , Prateek Hundekar , Tushar Gupta , Su Chen Fan
IPC分类号: H01L29/423 , H01L29/06 , H01L29/786 , H01L29/417 , H01L23/48 , H01L29/66 , H01L21/8234
CPC分类号: H01L29/42392 , H01L21/823412 , H01L21/823418 , H01L23/481 , H01L29/0665 , H01L29/41733 , H01L29/66742 , H01L29/78618 , H01L29/78696
摘要: A semiconductor device including a first nanodevice is located on a substrate, where the first nanodevice includes at least one channel. A first source/drain connected to the first nanodevice. A second nanodevice located on the substrate, where the second nanodevice includes at least one channel and a second source/drain connected to the second nanodevice. A first contact located above the first source/drain. A second contact located above the second source/drain. A contact cap located on top of the first contact and the second contact, where the contact cap has a first leg that extends downwards between the first contact and the second contact. The first leg of the contact cap is in contact with a first sidewall of the first contact, and a first sidewall of the second contact.
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公开(公告)号:US11688632B2
公开(公告)日:2023-06-27
申请号:US17136595
申请日:2020-12-29
发明人: Alex Joseph Varghese , Marc A. Bergendahl , Andrew M. Greene , Dallas Lea , Matthew T. Shoudy , Yann Mignot , Ekmini A. De Silva , Gangadhara Raja Muthinti
IPC分类号: H01L23/48 , H01L23/52 , H01L29/40 , H01L21/768
CPC分类号: H01L21/76829 , H01L21/7682 , H01L21/7688 , H01L21/76805 , H01L21/76844
摘要: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.
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公开(公告)号:US20230187516A1
公开(公告)日:2023-06-15
申请号:US17550658
申请日:2021-12-14
IPC分类号: H01L29/423 , H01L29/786 , H01L29/417 , H01L29/66 , H01L29/06
CPC分类号: H01L29/42392 , H01L29/78696 , H01L29/41775 , H01L29/66545 , H01L29/66553 , H01L29/0665 , H01L29/6656
摘要: A gate-all-around field effect transistor device is provided. The gate-all-around field effect transistor device includes one or more channel layers on a substrate. The gate-all-around field effect transistor device further includes an inner spacer wrapped around four sides of an end portion of each of the one or more channel layers. The gate-all-around field effect transistor device further includes a portion of an inner spacer liner between a portion of an upper most channel layer and a portion of an outer spacer.
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公开(公告)号:US20230102261A1
公开(公告)日:2023-03-30
申请号:US17485601
申请日:2021-09-27
发明人: Huimei Zhou , Andrew M. Greene , Julien Frougier , Ruqiang Bao , Jingyun Zhang , Miaomiao Wang , Dechao Guo
IPC分类号: H01L29/06 , H01L21/8234 , H01L29/786
摘要: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.
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公开(公告)号:US20220367626A1
公开(公告)日:2022-11-17
申请号:US17861960
申请日:2022-07-11
摘要: A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.
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公开(公告)号:US11424367B2
公开(公告)日:2022-08-23
申请号:US17124458
申请日:2020-12-16
发明人: Eric Miller , Julien Frougier , Yann Mignot , Andrew M. Greene
IPC分类号: H01L29/775 , H01L29/06 , H01L29/78 , H01L21/8234 , H01L21/768 , H01L29/66
摘要: A conformally deposited metal liner used for forming discrete, wrap-around contact structures is localized between pairs of gate structures and below the tops of the gate structures. Block mask patterning is employed to protect transistors over active regions of a substrate while portions of the metal liner between active regions are removed. A chamfering technique is employed to selectively remove further portions of the metal liner within the active regions. Metal silicide liners formed on the source/drain regions using the conformally deposited metal liner are electrically connected to source/drain contact metal following the deposition and patterning of a dielectric layer and subsequent metallization.
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公开(公告)号:US20210384296A1
公开(公告)日:2021-12-09
申请号:US17405455
申请日:2021-08-18
摘要: Semiconductor devices and methods of forming the same include recessing sacrificial layers in a stack of alternating sacrificial layers and channel layers using a first etch to form curved recesses at sidewalls of each sacrificial layer in the stack, with tails of sacrificial material being present at a top and bottom of each curved recess. Dielectric plugs are formed that each partially fill a respective curved recess, leaving exposed at least a portion of each tail of sacrificial material. The tails of sacrificial material are etched back using a second etch to expand the recesses. Inner spacers are formed in the expanded recesses.
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公开(公告)号:US20210151351A1
公开(公告)日:2021-05-20
申请号:US17136595
申请日:2020-12-29
发明人: Alex Joseph Varghese , Marc A. Bergendahl , Andrew M. Greene , Dallas Lea , Matthew T. Shoudy , Yann Mignot , Ekmini A. De Silva , Gangadhara Raja Muthinti
IPC分类号: H01L21/768
摘要: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.
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公开(公告)号:US20200303246A1
公开(公告)日:2020-09-24
申请号:US16359442
申请日:2019-03-20
发明人: Alex Joseph Varghese , Marc A. Bergendahl , Andrew M. Greene , Dallas Lea , Matthew T. Shoudy , Yann Mignot , Ekmini A. De Silva , Gangadhara Raja Muthinti
IPC分类号: H01L21/768
摘要: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.
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