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218 条记录 (耗时 0.03 秒)

    Silicide gate transistors
    41.
    发明授权
    Silicide gate transistors 有权
    硅化物栅极晶体管

    公开(公告)号：US06465309B1

    公开(公告)日：2002-10-15

    申请号：US09734185

    申请日：2000-12-12

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L21336

    CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

    摘要： A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.

    摘要翻译： 半导体结构及其制造方法提供由氧氮化物形成的栅极电介质或形成在凹部内的氮化物/氧化物堆叠。 非晶硅沉积在凹槽内的栅极电介质上，金属沉积在非晶硅上。 退火工艺在栅极电介质的凹槽内形成金属硅化物栅极。 可以选择更宽范围的金属材料，因为由氮氧化物或氮化物/氧化物堆叠形成的栅极电介质在硅化过程中保持稳定。 金属硅化物栅极显着降低了栅极和栅极端子之间的薄层电阻。

    Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process
    42.
    发明授权
    Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process 失效
    具有CVD非晶硅层的金属栅极和用于CMOS器件的硅化物和用替代栅极工艺制造的方法

    公开(公告)号：US06440868B1

    公开(公告)日：2002-08-27

    申请号：US09691259

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L21302

    CPC分类号： H01L21/28052 ,  H01L29/517 ,  H01L29/66545 ,  Y10S438/926

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后将金属沉积在CVD非晶硅层上。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

    Reduction of metal silicide/silicon interface roughness by dopant implantation processing
    43.
    发明授权
    Reduction of metal silicide/silicon interface roughness by dopant implantation processing 有权
    通过掺杂剂注入处理减少金属硅化物/硅界面粗糙度

    公开(公告)号：US06376343B1

    公开(公告)日：2002-04-23

    申请号：US09812695

    申请日：2001-03-21

    申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

    发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

    IPC分类号： H01L21425

    CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/665

    摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.

    摘要翻译： 避免了由于特定掺杂剂和金属硅化物的不良相容性而形成浅晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度，或至少大大降低 通过植入与金属硅化物具有相对良好的相容性的第一（主要）掺杂剂物质，使得其最大浓度在高于发生硅化反应的深度的深度处，并且注入具有相对较差相容性的第二（辅助）掺杂剂种类 金属硅化物，其中其最大浓度小于第一（主要）掺杂剂的最大浓度，并且处于低于发生硅化反应的深度的深度。 本发明特别适用于在掺杂Si的衬底上形成NiSi层。

    Process for fabricating a metal semiconductor device component by lateral oxidization
    45.
    发明授权
    Process for fabricating a metal semiconductor device component by lateral oxidization 有权
    通过侧面氧化制造金属半导体器件部件的工艺

    公开(公告)号：US06287918B1

    公开(公告)日：2001-09-11

    申请号：US09290086

    申请日：1999-04-12

    申请人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

    发明人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

    IPC分类号： H01L21336

    CPC分类号： H01L21/28079 ,  H01L21/28123 ,  H01L21/31683

    摘要： A process for fabricating a semiconductor device includes the formation of a metal device feature layer using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the metal device feature. The oxidation process is carried out by selectively, laterally oxidizing the metal composition of the device feature that overlies a dielectric layer. The lateral oxidation process forms metal oxide sidewall spacers on the device feature. Upon completion of the oxidation process, the metal oxide sidewall spacers are removed and a residual layer of unoxidized metal remains. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

    摘要翻译： 制造半导体器件的方法包括使用光刻技术形成金属器件特征层，随后进行氧化处理以减小金属器件特征的横向尺寸。 通过选择性地横向氧化覆盖在电介质层上的器件特征的金属组合物进行氧化过程。 横向氧化工艺在器件特征上形成金属氧化物侧壁间隔物。 氧化工艺完成后，去除金属氧化物侧壁间隔物，剩下残留的未氧化金属层。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

    Process for fabricating a high-endurance non-volatile memory device
    46.
    发明授权
    Process for fabricating a high-endurance non-volatile memory device 失效
    制造高耐久性非易失性存储器件的方法

    公开(公告)号：US06255169B1

    公开(公告)日：2001-07-03

    申请号：US09255053

    申请日：1999-02-22

    申请人： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

    发明人： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/11558

    摘要： A process for fabricating a non-volatile memory device includes the step of forming a nitrogen region in a semiconductor substrate prior to carrying out a thermal oxidation process to form a tunnel oxide layer. In a preferred process, nitrogen atoms are ion implanted into a silicon substrate to form a nitrogen region at the substrate surface. Then, a thermal oxidation process is carried out to grow a thin tunnel oxide layer overlying the surface of the nitrogen region. During the oxidation process, nitrogen is incorporated into the growing tunnel oxide layer. A floating-gate electrode is formed overlying the tunnel oxide layer and receives electrical charge transferred from a charge control region of the substrate through the tunnel oxide layer. The tunnel oxide layer is capable of undergoing repeated programming and erasing operations while exhibiting reduced effects from stress induced current leakage. In another aspect of the invention, an MOS transistor having enhanced carrier mobility is obtained by forming a gate oxide layer over a nitrogen region of a silicon substrate. The thermal oxidation process of the invention also provides both tunnel oxide layers and gate oxide layers having a reduced thickness for a given set of thermal oxidation conditions.

    摘要翻译： 一种用于制造非易失性存储器件的方法包括在进行热氧化工艺以形成隧道氧化物层之前在半导体衬底中形成氮区的步骤。 在优选的方法中，将氮原子离子注入到硅衬底中以在衬底表面形成氮区。 然后，进行热氧化处理，以生长覆盖在氮区域的表面上的薄的隧道氧化物层。 在氧化过程中，将氮气掺入生长的隧道氧化物层中。 在隧道氧化物层上形成浮栅电极，并接收通过隧道氧化物层从衬底的电荷控制区转移的电荷。 隧道氧化物层能够经受重复的编程和擦除操作，同时表现出应力感应电流泄漏的减小的影响。 在本发明的另一方面，通过在硅衬底的氮区上形成栅极氧化层，获得具有增强的载流子迁移率的MOS晶体管。 本发明的热氧化方法还为给定的一组热氧化条件提供具有减小的厚度的隧道氧化物层和栅极氧化物层。

    Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system
    48.
    发明授权
    Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system 有权
    半导体器件具有光刻系统的最小尺寸的分数维度的结构

    公开(公告)号：US09460924B2

    公开(公告)日：2016-10-04

    申请号：US11691332

    申请日：2007-03-26

    申请人： Witold P. Maszara ,  Qi Xiang

    发明人： Witold P. Maszara ,  Qi Xiang

    IPC分类号： H01L21/00 ,  H01L21/033

    CPC分类号： H01L21/0337

    摘要： A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.

    摘要翻译： 提供一种用于形成半导体器件的方法，包括处理具有间隔层和结构层的晶片，间隔层在结构层之上。 该方法继续，包括从间隔层形成第一侧壁间隔物，从第一侧壁间隔物下方的结构层形成结构带，在结构带上方形成掩模结构，并与结构带相交并形成从结构带下方的垂直柱 掩蔽结构。

    Programmable device with a metal oxide semiconductor field effect transistor
    49.
    发明授权
    Programmable device with a metal oxide semiconductor field effect transistor 有权
    具有金属氧化物半导体场效应晶体管的可编程器件

    公开(公告)号：US09196749B1

    公开(公告)日：2015-11-24

    申请号：US13341310

    申请日：2011-12-30

    申请人： Charu Sardana ,  Albert Ratnakumar ,  Qi Xiang ,  Bradley Jensen

    发明人： Charu Sardana ,  Albert Ratnakumar ,  Qi Xiang ,  Bradley Jensen

    IPC分类号： H01L29/66 ,  H01L29/788 ,  H01L27/112

    CPC分类号： H01L27/112 ,  H01L27/11206 ,  H01L29/66 ,  H01L29/7881

    摘要： A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.

    摘要翻译： 描述了由可编程衬底区域包围的具有金属氧化物半导体场效应晶体管（MOSFET）的可编程器件。 MOSFET具有由具有绝缘区域的沟道区域和设置在沟道区域上方的栅极分隔的源极和漏极区域。 设置在衬底区域内的接合部控制可编程衬底区域。 偏置连接点会耗尽衬底区域，从而将MOSFET的主体与次级阱隔离。 当结点保持不偏差时，MOSFET的主体电耦合到次级阱。