公开(公告)号：US07511358B2

公开(公告)日：2009-03-31

申请号：US11517595

申请日：2006-09-07

申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-gun Park

发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-gun Park

IPC分类号： H01L29/06

CPC分类号： H01L29/7923 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/7851 ,  H01L29/7887

摘要： Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same. The method includes forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region, forming sacrificial patterns having a groove to open a crossing region of the active region on the charge blocking layer, selectively removing portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer exposed by the opening groove using the sacrificial layer patterns as an etch mask to expose a top surface and side surfaces of the active region, forming a gate dielectric layer on exposed portion of the active region to cover exposed side surfaces of the of charge storage layer, forming a first gate on the gate dielectric layer to fill the groove, removing the sacrificial layer patterns, forming second gates on side surfaces of the first gate, forming isolated local charge storage patterns, charge blocking patterns and tunneling dielectric patterns by selectively removing exposed portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer, and forming a source/drain region on the active region.

摘要翻译： 提供一种具有多位存储器的非易失性存储器件及其制造方法。 该方法包括在鳍片活性区域上形成隧穿介质层，电荷存储层和电荷阻挡层，形成具有凹槽的牺牲图案，以打开电荷阻挡层上的有源区的交叉区域， 电荷阻挡层，电荷存储层和隧道电介质层，其使用牺牲层图案作为蚀刻掩模暴露于开口槽，以暴露有源区的顶表面和侧表面，在暴露部分上形成栅极电介质层 所述有源区域覆盖电荷存储层的暴露的侧表面，在栅极电介质层上形成第一栅极以填充沟槽，去除牺牲层图案，在第一栅极的侧表面上形成第二栅极，形成隔离的局部电荷 存储图案，电荷阻挡图案和隧道电介质图案，通过选择性地去除电荷阻挡层的暴露部分 r，电荷存储层和隧道电介质层，并且在有源区上形成源/漏区。

公开(公告)号：US20070268746A1

公开(公告)日：2007-11-22

申请号：US11657133

申请日：2007-01-24

申请人： Byung-yong Choi ,  Byung-gook Park ,  Dong-gun Park ,  Choong-ho Lee

发明人： Byung-yong Choi ,  Byung-gook Park ,  Dong-gun Park ,  Choong-ho Lee

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/7923

摘要： A nonvolatile memory device includes active regions extending in a word line direction in a semiconductor substrate and defined in a first zigzag pattern; gates extending in the word line direction and formed in a second zigzag pattern that repeatedly intersects the active regions in symmetry with the first zigzag pattern; a charge blocking layer, a charge storage layer and a tunnel dielectric layer below the gate; and source and drain regions each formed outside both sides of the gate.

摘要翻译： 非易失性存储器件包括在半导体衬底中沿着字线方向延伸并以第一曲折图形定义的有源区; 在所述字线方向上延伸并且形成为以与所述第一曲折图案对称的所述有源区域重复相交的第二曲折图案; 电荷阻挡层，电荷存储层和栅极下方的隧道电介质层; 并且源极和漏极区域均形成在栅极两侧的外侧。

公开(公告)号：US20060249779A1

公开(公告)日：2006-11-09

申请号：US11407133

申请日：2006-04-19

申请人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

发明人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851

摘要： In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate electrodes, formed at least at surface regions of the sidewalls of the fins between the source and the drain regions.

公开(公告)号：US20060154421A1

公开(公告)日：2006-07-13

申请号：US11329943

申请日：2006-01-11

申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed .on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

摘要翻译： 提供一种制造半导体器件的方法，通过该半导体器件，在半导体衬底的单元阵列区域中形成的单元晶体管采用其中使用间隔物形状的电极形成栅极和多位操作的结构 可以使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而优化以满足不同要求的结构的晶体管。 在该方法中，在单元阵列区域上形成单元晶体管。 单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜 沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。 在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。

公开(公告)号：US20050255656A1

公开(公告)日：2005-11-17

申请号：US11080731

申请日：2005-03-16

申请人： Hee-soo Kang ,  Dong-gun Park ,  Choong-ho Lee ,  Hye-jin Cho ,  Young-joon Ahn

发明人： Hee-soo Kang ,  Dong-gun Park ,  Choong-ho Lee ,  Hye-jin Cho ,  Young-joon Ahn

IPC分类号： H01L29/78 ,  H01L21/00 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/11 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7851

摘要： In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.

摘要翻译： 一方面，提供具有单元区域和外围电路区域的半导体基板，并且在半导体基板的单元区域和外围电路区域上形成掩模层。 通过在掩模层中形成第一开口以暴露半导体衬底的单元区域中的第一栅极区域，然后使用镶嵌工艺在第一开口中形成FinFET栅电极来制造FinFET栅极。 通过在掩模层中形成第二开口以暴露半导体衬底的外围电路区域中的第二栅极区域，然后使用镶嵌工艺在第二开口中形成MOSFET栅电极来制造MOSFET栅极。

公开(公告)号：US07804137B2

公开(公告)日：2010-09-28

申请号：US11930265

申请日：2007-10-31

申请人： Hee-soo Kang ,  Dong-gun Park ,  Choong-ho Lee ,  Hye-Jin Cho ,  Young-Joon Ahn

发明人： Hee-soo Kang ,  Dong-gun Park ,  Choong-ho Lee ,  Hye-Jin Cho ,  Young-Joon Ahn

IPC分类号： H01L23/62

CPC分类号： H01L29/785 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4908 ,  H01L29/66787 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.

摘要翻译： 一方面，提供具有单元区域和外围电路区域的半导体基板，并且在半导体基板的单元区域和外围电路区域上形成掩模层。 通过在掩模层中形成第一开口以暴露半导体衬底的单元区域中的第一栅极区域，然后使用镶嵌工艺在第一开口中形成FinFET栅电极来制造FinFET栅极。 通过在掩模层中形成第二开口以暴露半导体衬底的外围电路区域中的第二栅极区域，然后使用镶嵌工艺在第二开口中形成MOSFET栅电极来制造MOSFET栅极。

公开(公告)号：US07329581B2

公开(公告)日：2008-02-12

申请号：US11080731

申请日：2005-03-16

申请人： Hee-soo Kang ,  Dong-gun Park ,  Choong-ho Lee ,  Hye-jin Cho ,  Young-joon Ahn

发明人： Hee-soo Kang ,  Dong-gun Park ,  Choong-ho Lee ,  Hye-jin Cho ,  Young-joon Ahn

IPC分类号： H01L21/8234

CPC分类号： H01L27/11 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7851

摘要： In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.

摘要翻译： 一方面，提供具有单元区域和外围电路区域的半导体基板，并且在半导体基板的单元区域和外围电路区域上形成掩模层。 通过在掩模层中形成第一开口以暴露半导体衬底的单元区域中的第一栅极区域，然后使用镶嵌工艺在第一开口中形成FinFET栅电极来制造FinFET栅极。 通过在掩模层中形成第二开口以暴露半导体衬底的外围电路区域中的第二栅极区域，然后使用镶嵌工艺在第二开口中形成MOSFET栅电极来制造MOSFET栅极。

公开(公告)号：US20070054448A1

公开(公告)日：2007-03-08

申请号：US11517595

申请日：2006-09-07

申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-gun Park

发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-gun Park

IPC分类号： H01L21/8238

CPC分类号： H01L29/7923 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/7851 ,  H01L29/7887

摘要： Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same. The method includes forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region, forming sacrificial patterns having a groove to open a crossing region of the active region on the charge blocking layer, selectively removing portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer exposed by the opening groove using the sacrificial layer patterns as an etch mask to expose a top surface and side surfaces of the active region, forming a gate dielectric layer on exposed portion of the active region to cover exposed side surfaces of the of charge storage layer, forming a first gate on the gate dielectric layer to fill the groove, removing the sacrificial layer patterns, forming second gates on side surfaces of the first gate, forming isolated local charge storage patterns, charge blocking patterns and tunneling dielectric patterns by selectively removing exposed portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer, and forming a source/drain region on the active region.

摘要翻译： 提供一种具有多位存储器的非易失性存储器件及其制造方法。 该方法包括在鳍片活性区域上形成隧穿介质层，电荷存储层和电荷阻挡层，形成具有凹槽的牺牲图案，以打开电荷阻挡层上的有源区的交叉区域， 电荷阻挡层，电荷存储层和隧道电介质层，其使用牺牲层图案作为蚀刻掩模暴露于开口槽，以暴露有源区的顶表面和侧表面，在暴露部分上形成栅极电介质层 所述有源区域覆盖电荷存储层的暴露的侧表面，在栅极电介质层上形成第一栅极以填充沟槽，去除牺牲层图案，在第一栅极的侧表面上形成第二栅极，形成隔离的局部电荷 存储图案，电荷阻挡图案和隧道电介质图案，通过选择性地去除电荷阻挡层的暴露部分 r，电荷存储层和隧道电介质层，并且在有源区上形成源/漏区。

公开(公告)号：US07939408B2

公开(公告)日：2011-05-10

申请号：US12970475

申请日：2010-12-16

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US20110086483A1

公开(公告)日：2011-04-14

申请号：US12970475

申请日：2010-12-16

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。