公开(公告)号：US20070135297A1

公开(公告)日：2007-06-14

申请号：US11671794

申请日：2007-02-06

Applicant: Tae-Woo Woo ,  Myung-Ahn Ok ,  Jong-Sok Hahn ,  Mal-Ou Lee ,  Sang-Ook Kang ,  Sung-Bo Ko ,  Tae-Jin Kim ,  Sung-Kwan Kim

Inventor： Tae-Woo Woo ,  Myung-Ahn Ok ,  Jong-Sok Hahn ,  Mal-Ou Lee ,  Sang-Ook Kang ,  Sung-Bo Ko ,  Tae-Jin Kim ,  Sung-Kwan Kim

IPC: B01J31/00 ,  C08F4/44

CPC classification number: C07F17/00 ,  C08F4/65908 ,  C08F4/65912 ,  C08F10/00 ,  C08F110/02 ,  C08F210/16 ,  C08F2420/03 ,  C08F4/6592 ,  C08F2500/12 ,  C08F210/14

Abstract: Disclosed is an arylphenoxy catalyst system for producing an ethylene homopolymer or copolymers of ethylene and α-olefins, and a method of producing an ethylene homopolymer or copolymers of ethylene and α-olefins having a high molecular weight under a high temperature solution polymerization condition using the same. The catalyst system includes a group 4 arylphenoxy-based transition metal catalyst and an aluminoxane cocatalyst or a boron compound cocatalyst. In the transition metal catalyst, a cyclopentadiene derivative and arylphenoxide as fixed ligands are located around the group 4 transition metal, arylphenoxide is substituted with at least one aryl derivative and is located at the ortho position thereof, and the ligands are not crosslinked to each other. The catalyst includes non-toxic raw materials, synthesis of the catalyst is economical, and thermal stability of the catalyst is excellent. It is useful for producing an ethylene homopolymer or copolymers of ethylene and α-olefins having various physical properties in commercial polymerization processes.

Abstract translation: 公开了用于生产乙烯均聚物或乙烯与α-烯烃的共聚物的芳基苯氧基催化剂体系，以及在高温溶液聚合条件下使用高温溶液聚合条件制备乙烯均聚物或乙烯与α-烯烃的共聚物的方法， 相同。 该催化剂体系包括基团4芳基苯氧基基过渡金属催化剂和铝氧烷助催化剂或硼化合物助催化剂。 在过渡金属催化剂中，作为固定配体的环戊二烯衍生物和芳基苯氧基位于第4族过渡金属周围，芳基酚被至少一个芳基衍生物取代，位于其邻位，并且配体彼此不交联 。 催化剂包括无毒原料，催化剂的合成是经济的，催化剂的热稳定性优异。 在商业聚合方法中生产具有各种物理性质的乙烯均聚物或乙烯和α-烯烃的共聚物是有用的。

公开(公告)号：US5838990A

公开(公告)日：1998-11-17

申请号：US905562

申请日：1997-08-04

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F9/00 ,  G06F13/16

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5835956A

公开(公告)日：1998-11-10

申请号：US822148

申请日：1997-03-17

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F13/16

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5703828A

公开(公告)日：1997-12-30

申请号：US580622

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US09123852B2

公开(公告)日：2015-09-01

申请号：US13788169

申请日：2013-03-07

Applicant: Jae-Hyeon Jeon ,  Tae-Jin Kim ,  Hae-Kwan Seo

Inventor： Jae-Hyeon Jeon ,  Tae-Jin Kim ,  Hae-Kwan Seo

IPC: G01L1/20 ,  H01L33/08 ,  G01L1/00 ,  G01L5/04 ,  G09G3/32 ,  G06F3/041 ,  G06F1/16 ,  G06F3/045

CPC classification number: H01L33/08 ,  G01L1/005 ,  G01L1/205 ,  G01L5/04 ,  G06F1/1652 ,  G06F3/041 ,  G06F3/0412 ,  G06F3/0414 ,  G06F3/045 ,  G09G3/006 ,  G09G3/3208 ,  G09G2380/02 ,  H01L2251/5338

Abstract: A method of manufacturing a flexible display device for sensing bending that includes forming a lower electrode layer, which includes a plurality of lower electrodes spaced apart from each other on a substrate, forming an insulation layer on the lower electrode layer, forming holes in the insulation layer to expose at least a part of each of the plurality of lower electrodes, and forming an upper electrode layer, which includes a plurality of upper electrodes that are spaced apart from each other on the insulation layer and that fill the holes in the insulation layer. At least two conductive units including the lower electrode layer, the insulation layer, and the upper electrode layer are formed to face each other on a substrate of a non-display unit that is arranged near a boundary of the display device.

Abstract translation: 一种制造用于感测弯曲的柔性显示装置的方法，包括形成下电极层，所述下电极层包括在基板上彼此间隔开的多个下电极，在所述下电极层上形成绝缘层，在所述绝缘层中形成孔 以暴露多个下电极中的每一个的至少一部分，并且形成上电极层，其包括在绝缘层上彼此间隔开并且填充绝缘层中的孔的多个上电极 。 在布置在显示装置的边界附近的非显示单元的基板上形成包括下电极层，绝缘层和上电极层的至少两个导电单元彼此面对。

公开(公告)号：US20130194248A1

公开(公告)日：2013-08-01

申请号：US13529515

申请日：2012-06-21

Applicant: Tae-Jin Kim

Inventor： Tae-Jin Kim

IPC: G09G3/32 ,  G09G5/00

CPC classification number: G09G3/3233 ,  G09G3/3659 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2320/045

Abstract: A method of driving a pixel circuit includes initializing a driving transistor and a storage capacitor by simultaneously applying an initialization voltage and a first power voltage to a gate electrode of the driving transistor and the storage capacitor, respectively, diode-coupling the driving transistor, applying a data voltage to the storage capacitor, applying the data voltage to the gate electrode of the driving transistor by a coupling of a compensation capacitor coupled between the gate electrode of the driving transistor and the storage capacitor, and applying a current corresponding to the first power voltage and the data voltage to an organic light emitting diode that is coupled to the driving transistor.

Abstract translation: 驱动像素电路的方法包括：通过同时对驱动晶体管和存储电容器的栅电极施加初始化电压和第一电源电压来初始化驱动晶体管和存储电容器，二极管耦合驱动晶体管，施加 向存储电容器提供数据电压，通过耦合在驱动晶体管的栅电极和存储电容器之间的补偿电容器的耦合将数据电压施加到驱动晶体管的栅电极，并施加与第一功率相对应的电流 电压和与耦合到驱动晶体管的有机发光二极管的数据电压。

公开(公告)号：US08344081B2

公开(公告)日：2013-01-01

申请号：US12808257

申请日：2008-10-30

Applicant: Jong-Sok Hahn ,  Myung-Ahn Ok ,  Dong-Cheol Shin ,  Ho-Seong Lee ,  Sang-Ook Kang ,  Tae-Jin Kim

Inventor： Jong-Sok Hahn ,  Myung-Ahn Ok ,  Dong-Cheol Shin ,  Ho-Seong Lee ,  Sang-Ook Kang ,  Tae-Jin Kim

IPC: C08F4/643 ,  C08F4/6592 ,  B01J31/22 ,  C07F17/00

CPC classification number: C07F17/00

Abstract: The present invention relates to a transition metal complex useful as a transition metal catalyst in the preparation of an ethylene homopolymer or a copolymer of ethylene and an α-olefin, a catalyst composition comprising the same and a process of preparing an ethylene homopolymer or a copolymer of ethylene and an α-olefin using the same. More particularly, it relates to a transition metal complex having a cyclopentadiene derivative and at least one phenyl oxide ligand substituted at the 2-position of phenyl with, for example, a silyl group having a C1-C30 hydrocarbon group or a C1-C20 hydrocarbon group, around a group IV transition metal, with no crosslinkage between the ligands, a catalyst composition comprising the transition metal complex and a cocatalyst selected from the group consisting of an aluminoxane and a boron compound, and a process for preparing an ethylene homopolymer or a copolymer of ethylene and an α-olefin using the same.

Abstract translation: 本发明涉及在乙烯均聚物或乙烯与α-烯烃的共聚物的制备中用作过渡金属催化剂的过渡金属络合物，包含该过渡金属络合物的催化剂组合物和制备乙烯均聚物或共聚物的方法 的乙烯和使用其的α-烯烃。 更具体地说，本发明涉及具有环戊二烯衍生物和至少一个苯基氧化物配位体的过渡金属络合物，其在苯基的2-位被取代，例如具有C 1 -C 30烃基或C 1 -C 20烃的甲硅烷基 在IV族过渡金属周围，配体之间没有交联，包含过渡金属配合物的催化剂组合物和选自铝氧烷和硼化合物的助催化剂，以及制备乙烯均聚物或 乙烯与使用其的α-烯烃的共聚物。

公开(公告)号：US08301924B2

公开(公告)日：2012-10-30

申请号：US12587826

申请日：2009-10-14

Applicant: Tae-Jin Kim ,  Jung-Hun Park ,  Hyuk-Chan Park ,  Ho-Seung Lee ,  Kang-Min Lee

Inventor： Tae-Jin Kim ,  Jung-Hun Park ,  Hyuk-Chan Park ,  Ho-Seung Lee ,  Kang-Min Lee

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A portable communication apparatus is configured to perform a method for power control of a Central Processing Unit (CPU) in a portable communication apparatus. The portable communication apparatus for power control of the CPU includes a CPU configured to report an operation status of the CPU and an overhead determiner. The CPU is also configured to change a power control level according to control of the overhead determiner. The overhead determiner is configured to determine an overhead of the CPU and to control the power control level of the CPU based on the overhead of the CPU.

Abstract translation: 便携式通信装置被配置为执行便携式通信装置中的中央处理单元（CPU）的功率控制方法。 用于CPU的功率控制的便携式通信装置包括CPU，CPU被配置为报告CPU的操作状态和开销确定器。 CPU还被配置为根据开销确定器的控制来改变功率控制级别。 开销确定器被配置为确定CPU的开销并且基于CPU的开销来控制CPU的功率控制级别。

公开(公告)号：US20120091477A1

公开(公告)日：2012-04-19

申请号：US13050176

申请日：2011-03-17

Applicant: Tae-Jin Kim

Inventor： Tae-Jin Kim

IPC: H01L51/52

CPC classification number: H01L51/5246 ,  H01L51/5256

Abstract: An organic light emitting diode (OLED) display comprises: a substrate; a display unit formed on the substrate and including an organic light emitting element; an interception layer positioned at the outside of the display unit on the substrate; and a thin film encapsulation layer which is formed with a stacked film of an inorganic film and an organic film, which has an end portion contacting the interception layer, and which covers the entire display unit and at least a part of the interception layer.

Abstract translation: 有机发光二极管（OLED）显示器包括：基板; 形成在所述基板上并包括有机发光元件的显示单元; 位于所述显示单元的所述外部的基板上的截取层; 和形成有无机膜和有机膜的叠层膜的薄膜封装层，其具有与截取层接触的端部，并且覆盖整个显示单元和截取层的至少一部分。

公开(公告)号：US07942506B2

公开(公告)日：2011-05-17

申请号：US12112170

申请日：2008-04-30

Applicant: Sung Joon Park ,  Tae-Jin Kim ,  Young Hye Park ,  Dai Geun Kim

Inventor： Sung Joon Park ,  Tae-Jin Kim ,  Young Hye Park ,  Dai Geun Kim

IPC: B41J2/05

CPC classification number: B41J2/14129 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1645 ,  B41J2002/14387 ,  Y10T29/49401

Abstract: An inkjet printer head includes a substrate, an insulating layer having a groove and disposed on the substrate, a heating member having a concavely curved upper surface and disposed on an upper portion of the groove, an electrode to make contact with the heating member to apply electric current to the heating member, a chamber layer disposed on the heating member, and a nozzle layer having one or more nozzles and disposed on the chamber layer. According to the inkjet printer head, the heating member has a curved structure to increase a length of the heating member, so that resistance of the heating member can be increased. Thus, the heating member can stably operate regardless of current variation applied thereto, and the printing work can be performed.

Abstract translation: 一种喷墨打印机头，包括：基板，具有凹槽并设置在基板上的绝缘层，具有凹曲面上表面并设置在凹槽上部的加热部件，与加热部件接触的电极 设置在加热构件上的电流，设置在加热构件上的室层，以及具有一个或多个喷嘴并设置在室层上的喷嘴层。 根据喷墨打印机头，加热部件具有弯曲结构，以增加加热部件的长度，从而能够提高加热部件的电阻。 因此，无论施加电流变化如何，加热构件都可以稳定地操作，并且可以执行打印作业。