公开(公告)号：US06992909B2

公开(公告)日：2006-01-31

申请号：US11157318

申请日：2005-06-20

申请人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

发明人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

IPC分类号： G11C17/00

CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

公开(公告)号：US20060017084A1

公开(公告)日：2006-01-26

申请号：US10897045

申请日：2004-07-22

申请人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William Saiki ,  Hieu Tran ,  Dana Lee

发明人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William Saiki ,  Hieu Tran ,  Dana Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/0805 ,  H01L27/0811 ,  H01L29/94

摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

摘要翻译： 集成的MIS电容器具有两个基本相同的MIS电容器。 第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。 半导体衬底具有第二导电类型。 栅电极与第一电容器的沟道区隔离并隔开。 第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。 第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。 以这种方式，电容器以反并联配置连接。 具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。

公开(公告)号：US06940125B2

公开(公告)日：2005-09-06

申请号：US10407627

申请日：2003-04-04

申请人： Sohrab Kianian ,  Dana Lee

发明人： Sohrab Kianian ,  Dana Lee

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7926

摘要： Vertical NROM devices are made in a substantially single crystalline silicon substrate having a planar surface. The vertical NROM cell and device has a first region and a second region spaced apart from one another by a channel. A dielectric is spaced apart from the channel to capture charges injected from the channel onto the dielectric. A gate is positioned over the dielectric and spaced apart therefrom and controls the flow of current through the channel. In the improvement of the present invention, a portion of the channel is substantially perpendicular to the top planar surface of the substrate. Methods for making the vertical NROM cell and array are also disclosed.

摘要翻译： 垂直NROM器件制成具有平坦表面的基本单晶硅衬底。 垂直NROM单元和器件具有通过通道彼此间隔开的第一区域和第二区域。 电介质与通道间隔开以捕获从通道注入到电介质上的电荷。 栅极位于电介质上并与其间隔开并控制通过通道的电流。 在本发明的改进中，通道的一部分基本上垂直于基板的顶部平坦表面。 还公开了制造垂直NROM单元和阵列的方法。

公开(公告)号：US20050104116A1

公开(公告)日：2005-05-19

申请号：US10714243

申请日：2003-11-13

申请人： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

发明人： Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

摘要翻译： 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。

公开(公告)号：US06822287B1

公开(公告)日：2004-11-23

申请号：US10452027

申请日：2003-05-30

申请人： Dana Lee ,  Yaw Wen Hu

发明人： Dana Lee ,  Yaw Wen Hu

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  G11C5/063 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42336 ,  H01L29/7885

摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns where each cell has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges between the first region and the second region. A first plurality of row lines electrically connect the second region of cells in the same row. A plurality of column lines electrically connect the first region of cells in the same column. A plurality of strap lines connect certain of the row lines with each strap line electrically connecting a second plurality of row lines not immediately adjacent to one another, wherein row lines connected to a first strap line are interleaved with row lines connected to a second strap line.

摘要翻译： 非易失性存储单元的阵列被布置在多个行和列中，其中每个单元具有第一区域和彼此间隔开的第二区域，其间具有沟道区域，用于在第一区域和第二区域之间传导电荷 地区。 第一组多条行线电连接同一行中的第二区域的单元。 多个列线电连接同一列中的第一区域的单元。 多条绑带线连接某些行线，每条绑带线电连接彼此不紧邻的第二多条行线，其中连接到第一绑带线的行线与连接到第二绑带线的行线交错 。

公开(公告)号：US06806531B1

公开(公告)日：2004-10-19

申请号：US10409248

申请日：2003-04-07

申请人： Bomy Chen ,  Dana Lee ,  Bing Yeh

发明人： Bomy Chen ,  Dana Lee ,  Bing Yeh

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66825

摘要： A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region. A bi-directional non-volatile memory cell has two floating gates each formed in a cavity. A method of making the non-volatile memory cell and the array are also disclosed.

公开(公告)号：US06329685B1

公开(公告)日：2001-12-11

申请号：US09401173

申请日：1999-09-22

申请人： Dana Lee

发明人： Dana Lee

IPC分类号： H01L2972

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates. A bit line is formed in the bit line direction contacting the second region in the space between the control gates.

摘要翻译： 在半导体衬底中形成浮动栅极存储单元的半导体存储器阵列的自对准方法在基板上具有基本上彼此平行的多个间隔开的隔离区域。 有源区域位于每对相邻隔离区域之间。 活性隔离区域和平行区域形成为平行且在列方向。 在行方向上，形成间隔开的氮化硅的条。 源极线插塞形成在相邻的氮化硅对之间并且与有源区域中的第一区域以及隔离区域接触。 去除氮化硅条并进行各向同性蚀刻。 此外，氮化硅下方的材料也被各向同性地蚀刻。 然后在平行于源极线插塞并与浮动栅极相邻的行方向上形成多晶硅间隔物。 第二区域形成在相邻的间隔开的控制门之间。 在与控制栅极之间的空间中的第二区域接触的位线方向上形成位线。

公开(公告)号：US08687421B2

公开(公告)日：2014-04-01

申请号：US13435476

申请日：2012-03-30

申请人： Chris Avila ,  Jianmin Huang ,  Dana Lee

发明人： Chris Avila ,  Jianmin Huang ,  Dana Lee

IPC分类号： G11C16/00

CPC分类号： G06F11/1048 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/5634

摘要： The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected.

摘要翻译： 是否刷新或退出内存块的决定是基于正在使用的一组动态读取值。 在使用动态读取值表的存储器系统中，该表被配置为包括如何处理读取错误（退出，刷新）以及不同动态读取情况的读取参数。 在细化中，读取案例编号可用于对被选择进行刷新或退出的块进行优先级排序。 在读取擦除更精确的情况下，可以应用多个动态读取情况。 此外，可以智能地选择应用哪些情况。

公开(公告)号：US08472266B2

公开(公告)日：2013-06-25

申请号：US13077778

申请日：2011-03-31

申请人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

发明人： Anubhav Khandelwal ,  Jun Wan ,  Shih-Chung Lee ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418

摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.

摘要翻译： 公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。 技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。 例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。 在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。 将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

公开(公告)号：US20130051148A1

公开(公告)日：2013-02-28

申请号：US13214765

申请日：2011-08-22

申请人： Dana Lee ,  Ken Oowada

发明人： Dana Lee ,  Ken Oowada

IPC分类号： G11C16/10

CPC分类号： G11C16/3427 ,  G11C11/5642

摘要： Read compensation for partially programmed blocks of non-volatile storage is provided. In partially programmed blocks, the threshold voltage distributions may be shifted down relative to their final positions. Upon receiving a request to read a page that is stored in a block, a determination may be made whether the block is partially programmed. If so, then a suitable compensation may be made when reading the requested page. This compensation may compensate for the non-volatile storage elements (or pages) in the block that have not yet been programmed. The amount of compensation may be based on the amount of interference that would be caused to the requested page by later programming of the other pages. The compensation may compensate for shifts in threshold voltage distributions of the requested page that would occur from later programming of other pages.

摘要翻译： 提供了部分编程的非易失性存储块的读取补偿。 在部分编程的块中，阈值电压分布可以相对于其最终位置向下移动。 在接收到读取存储在块中的页面的请求时，可以确定块是否被部分编程。 如果是这样，那么在阅读请求的页面时可以做出适当的补偿。 该补偿可以补偿块中尚未编程的非易失性存储元件（或页）。 补偿金额可以基于通过稍后对其他页面进行编程而对所请求的页面造成的干扰量。 该补偿可以补偿所请求的页面的阈值电压分布的变化，其将从其他页面的后续编程发生。